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Rethinking Memory Permissions for Protection Against Cross-Layer Attacks

Published: 08 December 2015 Publication History

Abstract

The inclusive permissions structure (e.g., the Intel ring model) of modern commodity CPUs provides privileged system software layers with arbitrary permissions to access and modify client processes, allowing them to manage these clients and the system resources efficiently. Unfortunately, these inclusive permissions allow a compromised high-privileged software layer to perform arbitrary malicious activities. In this article, our goal is to prevent attacks that cross system layers while maintaining the abilities of system software to manage the system and allocate resources. In particular, we present a hardware-supported page permission framework for physical pages that is based on the concept of noninclusive sets of memory permissions for different layers of system software (such as hypervisors, operating systems, and user-level applications). Instead of viewing privilege levels as an ordered hierarchy with each successive level being more privileged, we view them as distinct levels each with its own set of permissions. In order to enable system software to manage client processes, we define a set of legal permission transitions that support resource allocation but preserve security. We show that the model prevents a range of recent attacks. We also show that it can be implemented with negligible performance overhead (both at load time and at runtime), low hardware complexity, and minimal changes to the commodity OS and hypervisor code.

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Cited By

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  • (2017)Hardening extended memory access control schemes with self-verified address spacesProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199752(392-399)Online publication date: 13-Nov-2017
  • (2017)Hardening extended memory access control schemes with self-verified address spaces2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203804(392-399)Online publication date: Nov-2017
  • (2016)Understanding and Mitigating Covert Channels Through Branch PredictorsACM Transactions on Architecture and Code Optimization10.1145/287063613:1(1-23)Online publication date: 7-Mar-2016

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Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 12, Issue 4
January 2016
848 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/2836331
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 08 December 2015
Accepted: 01 November 2015
Revised: 01 October 2015
Received: 01 April 2014
Published in TACO Volume 12, Issue 4

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Author Tags

  1. Architecture
  2. security
  3. system software

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Cited By

View all
  • (2017)Hardening extended memory access control schemes with self-verified address spacesProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199752(392-399)Online publication date: 13-Nov-2017
  • (2017)Hardening extended memory access control schemes with self-verified address spaces2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203804(392-399)Online publication date: Nov-2017
  • (2016)Understanding and Mitigating Covert Channels Through Branch PredictorsACM Transactions on Architecture and Code Optimization10.1145/287063613:1(1-23)Online publication date: 7-Mar-2016

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