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Enabling Hybrid PCM Memory System with Inherent Memory Management

Published: 11 October 2016 Publication History

Abstract

Replacing the traditional volatile main memory, e.g., DRAM, with a non-volatile phase change memory (PCM) has become a possible solution to reduce the energy consumption of computing systems. To further reduce the bit cost of PCM, the development trend of PCM goes from single-level-cell (SLC) the multi-level-cell (MLC) technology. However, the worse endurance and the intolerable long write latency hinder a MLC PCM from being used as the main memory of computing systems. In this work, we propose a memory management design to facilitate enabling the use of hybrid PCMas main memory to achieve a better trade-off between the cost and the performance of PCM-based computing systems, where the hybrid PCM is composed of SLC PCM and MLC PCM. In particular, the proposed design can be seamlessly integrated into the inherent memory management of modern operation systems without additional hardware components. The evaluation results show that the proposed design over a hybrid PCM can improve the average read/write performance for almost 10 times and extend the lifetime for more than 32 times, compared to systems with pure MLC PCM.

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Cited By

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  • (2021)A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)10.1109/ITC-CSCC52171.2021.9501266(1-4)Online publication date: 27-Jun-2021
  • (2020)UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292536639:9(1792-1805)Online publication date: Sep-2020

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cover image ACM Conferences
RACS '16: Proceedings of the International Conference on Research in Adaptive and Convergent Systems
October 2016
266 pages
ISBN:9781450344555
DOI:10.1145/2987386
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 October 2016

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Author Tags

  1. endurance
  2. memory management
  3. phase change memory
  4. wear leveling

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RACS '16 Paper Acceptance Rate 40 of 161 submissions, 25%;
Overall Acceptance Rate 393 of 1,581 submissions, 25%

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View all
  • (2021)A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)10.1109/ITC-CSCC52171.2021.9501266(1-4)Online publication date: 27-Jun-2021
  • (2020)UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292536639:9(1792-1805)Online publication date: Sep-2020

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