research-article

Automatic Cell Layout in the 7nm Era

Authors:

Stefan Hougardy,

Jannik SilvanusAuthors Info & Claims

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

Pages 99 - 106

https://doi.org/10.1145/3036669.3036672

Published: 19 March 2017 Publication History

Abstract

Multi patterning technology used in 7nm technology and beyond imposes more and more complex design rules on the layout of cells. The often non local nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for the automatic cell layout that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but simultaneously optimizes the routability of the cell and finds a best folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. In a first step it computes an electrically correct routing using a mixed integer programming formulation. To improve yield and optimize DFM, additional constraints are added to this model.

We present experimental results on current 7nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. Our algorithms are currently used for the design of 7nm cells at a leading chip manufacturer where they improved manufacturability and led to reduced turnaround times.

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Cited By

Hentschke RBehjat LYang S(2022)Physical Design at the Transistor Level Beyond Standard-Cell MethodologyProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3511476(141-143)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3511476
Li YLin SNishizawa SSu HFong MChen OOnodera H(2022)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid MapIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316733941:12(5568-5581)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3167339
Cheng CKahng AKim HKim MLee DPark DWoo M(2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3093015
Show More Cited By

Index Terms

Automatic Cell Layout in the 7nm Era
1. Hardware

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cover image ACM Conferences

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

March 2017

176 pages

ISBN:9781450346962

DOI:10.1145/3036669

General Chair:
Mustafa Ozdal
Bilkent University
,
Program Chair:
Chris Chu
Iowa State University

Copyright © 2017 ACM.

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Publication History

Published: 19 March 2017

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ISPD '17: International Symposium on Physical Design

March 19 - 22, 2017

Oregon, Portland, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Hentschke RBehjat LYang S(2022)Physical Design at the Transistor Level Beyond Standard-Cell MethodologyProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3511476(141-143)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3511476
Li YLin SNishizawa SSu HFong MChen OOnodera H(2022)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid MapIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316733941:12(5568-5581)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3167339
Cheng CKahng AKim HKim MLee DPark DWoo M(2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3093015
Cheng CHo CLee DLin BPark D(2021)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMTIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306563929:6(1178-1191)Online publication date: Jun-2021
https://doi.org/10.1109/TVLSI.2021.3065639
Cheng CHo CLee DLin B(2021)Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)IEEE Journal on Exploratory Solid-State Computational Devices and Circuits10.1109/JXCDC.2021.30927697:1(43-51)Online publication date: Jun-2021
https://doi.org/10.1109/JXCDC.2021.3092769
Park DLee DKang IHoltz CGao SLin BCheng C(2020)Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design RulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977066(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.2977066
Van Cleeff PHougardy SSilvanus JWerner T(2020)BonnCell: Automatic Cell Layout in the 7-nm EraIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.296278239:10(2872-2885)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2962782
Cheng CLee DPark D(2020)Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180592(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180592
Li YLin SNishizawa SSu HFong MChen OOnodera H(2019)NCTUcellProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317868(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317868
Park DKang IKim YGao SLin BCheng CBustany ISwartz W(2019)ROADProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309752(65-72)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3299902.3309752
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