research-article

Moonwalk: NRE Optimization in ASIC Clouds

Authors:

Moein Khazraee,

Michael Bedford TaylorAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 45, Issue 1

Pages 511 - 526

https://doi.org/10.1145/3093337.3037749

Published: 04 April 2017 Publication History

Abstract

Cloud services are becoming increasingly globalized and data-center workloads are expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in power and performance by accelerating compute-intensive workloads. ASIC-based clouds are a promising way to optimize the Total Cost of Ownership (TCO) of a given datacenter computation (e.g. YouTube transcoding) by reducing both energy consumption and marginal computation cost.

The feasibility of an ASIC Cloud for a particular application is directly gated by the ability to manage the Non-Recurring Engineering (NRE) costs of designing and fabricating the ASIC, so that it is significantly lower (e.g. 2X) than the TCO of the best available alternative.

In this paper, we show that technology node selection is a major tool for managing ASIC Cloud NRE, and allows the designer to trade off an accelerator's excess energy efficiency and cost performance for lower total cost.

We explore NRE and cross-technology optimization of ASIC Clouds for four different applications: Bitcoin mining, YouTube-style video transcoding, Litecoin, and Deep Learning. We address these challenges and show large reductions in the NRE, potentially enabling ASIC Clouds to address a wider variety of datacenter workloads. Our results suggest that advanced nodes like 16nm will lead to sub-optimal TCO for many workloads, and that use of older nodes like 65nm can enable a greater diversity of ASIC Clouds.

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Index Terms

Moonwalk: NRE Optimization in ASIC Clouds
1. Computer systems organization
  1. Architectures
    1. Distributed architectures
      1. Cloud computing
2. Hardware

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 45, Issue 1

Asplos'17

March 2017

812 pages

ISSN:0163-5964

DOI:10.1145/3093337

Editor:
Babak Falsafi
Interim

Issue’s Table of Contents

ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
April 2017
856 pages
ISBN:9781450344654
DOI:10.1145/3037697
General Chairs:
Yunji Chen
Institute of Computing Technology, CAS, China
,
Olivier Temam
Google, USA
,
Program Chair:
John Carter
IBM, USA

Copyright © 2017 ACM.

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Published: 04 April 2017

Published in SIGARCH Volume 45, Issue 1

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https://doi.org/10.23919/ICS.2024.3451428
Li FWang YWang YWang MHan YLi HLi XKim T(2024)Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet IntegrationProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473888(58-64)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473888
Agrawal RDe Castro LJuvekar CChandrakasan AVaikuntanathan VJoshi A(2023)MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic EncryptionProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614302(685-697)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614302
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