research-article

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems

Authors:

Shuming ChenAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 5s

Article No.: 162, Pages 1 - 21

https://doi.org/10.1145/3126561

Published: 27 September 2017 Publication History

Abstract

In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access performance among different nodes. This phenomenon may lead to high latencies for some DRAM accesses that become the performance bottleneck of the system. The paper addresses the DRAM access fairness problem in 3D NoC-based many-core systems by narrowing the latency difference of DRAM accesses as well as reducing the maximum latency. Firstly, the latency of a round-trip DRAM access is modeled and the factors causing DRAM access latency difference are discussed in detail. Secondly, the DRAM access fairness is further quantitatively analyzed through experiments. Thirdly, we propose to predict the network latency of round-trip DRAM accesses and use the predicted round-trip DRAM access time as the basis to prioritize the DRAM accesses in DRAM interfaces so that the DRAM accesses with potential high latencies can be transferred as early and fast as possible, thus achieving fair DRAM access. Experiments with synthetic and application workloads validate that our approach can achieve fair DRAM access and outperform the traditional First-Come-First-Serve (FCFS) scheduling policy and the scheduling policies proposed by reference [7] and [24] in terms of maximum latency, Latency Standard Deviation (LSD)1 and speedup. In the experiments, the maximum improvement of the maximum latency, LSD, and speedup are 12.8%, 6.57%, and 8.3% respectively. Besides, our proposal brings very small extra hardware overhead (<0.6%) in comparison to the three counterparts.

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Cited By

Wang BLu Z(2022)Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309141041:5(1523-1536)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3091410
Wang BLu Z(2020)Advance Virtual Channel ReservationIEEE Transactions on Computers10.1109/TC.2020.297198269:9(1320-1334)Online publication date: 1-Sep-2020
https://doi.org/10.1109/TC.2020.2971982
Wang BLu Z(2020)Supporting QoS in AXI4 Based Communication Architecture2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00008(548-553)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00008
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Index Terms

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
      1. Embedded hardware
    2. System on a chip
2. Hardware
  1. Very large scale integration design
    1. Design reuse and communication-based design
      1. Network on chip
      2. System on a chip

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 16, Issue 5s

Special Issue ESWEEK 2017, CASES 2017, CODES + ISSS 2017 and EMSOFT 2017

October 2017

1448 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3145508

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

Issue’s Table of Contents

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 September 2017

Accepted: 01 June 2017

Revised: 01 May 2017

Received: 01 March 2017

Published in TECS Volume 16, Issue 5s

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National Natural Science Foundation of China
Cooperative Innovation Center of high-performance computing
Hunan Natural Science Foundation of China

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Cited By

Wang BLu Z(2022)Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309141041:5(1523-1536)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3091410
Wang BLu Z(2020)Advance Virtual Channel ReservationIEEE Transactions on Computers10.1109/TC.2020.297198269:9(1320-1334)Online publication date: 1-Sep-2020
https://doi.org/10.1109/TC.2020.2971982
Wang BLu Z(2020)Supporting QoS in AXI4 Based Communication Architecture2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00008(548-553)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00008
Wang BLu Z(2019)Advance Virtual Channel Reservation2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715104(1178-1183)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715104

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