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Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC

Published: 19 October 2017 Publication History

Abstract

Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-dimensional (3D) manycore systems. The associated design challenges and the trade-offs of the NFIC-based vertical links depend on achievable data-rates, energy and area overheads. In this work, we propose a holistic design flow that explores optimum energy and area efficient NFIC-link design as a communication backbone in a 3D manycore chip. Moreover, the design framework employs statistical link analysis to select optimum NFIC link configuration. The proposed NFIC-link design is significantly more efficient in terms of energy efficiency and area overhead compared to state-of-the-art counterpart. Energy efficiency and resiliency of NFIC-links are exploited in the context of a 3D NoC design. We demonstrate that overall reliability of the NFIC-enabled 3D NoC is significantly better compared to a conventional stand-alone TSV-based architecture.

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Cited By

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  • (2021)Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW53999.2021.00055(292-296)Online publication date: Nov-2021
  • (2020)A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoCIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.301309267:11(3919-3932)Online publication date: Nov-2020
  • (2020)Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST51057.2020.9358256(1-6)Online publication date: 15-Dec-2020
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      cover image ACM Conferences
      NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip
      October 2017
      170 pages
      ISBN:9781450349840
      DOI:10.1145/3130218
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 19 October 2017

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      Author Tags

      1. 3D IC
      2. 3D NoC
      3. Geometric Programming
      4. Low power
      5. NFIC
      6. Optimization
      7. Proximity Communication
      8. Robust NoC design

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      • Research-article
      • Research
      • Refereed limited

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      NOCS '17
      NOCS '17: International Symposium on Networks-on-Chip
      October 19 - 20, 2017
      Seoul, Republic of Korea

      Acceptance Rates

      NOCS '17 Paper Acceptance Rate 14 of 44 submissions, 32%;
      Overall Acceptance Rate 14 of 44 submissions, 32%

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      Cited By

      View all
      • (2021)Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW53999.2021.00055(292-296)Online publication date: Nov-2021
      • (2020)A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoCIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.301309267:11(3919-3932)Online publication date: Nov-2020
      • (2020)Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST51057.2020.9358256(1-6)Online publication date: 15-Dec-2020
      • (2019)Sparse 3-D NoCs with Inductive CouplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317913(1-6)Online publication date: 2-Jun-2019
      • (2019)Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process2019 Seventh International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW.2019.00054(269-274)Online publication date: Nov-2019
      • (2019)Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058859(1-6)Online publication date: Oct-2019
      • (2018)High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286570426:12(2921-2934)Online publication date: Dec-2018
      • (2018)A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-ChipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285689026:11(2406-2418)Online publication date: Nov-2018
      • (2018)An Echo-Canceller-Iess NFIC- TSV Hybrid 3D Interconnect for Simultaneous Bidirectional Vertical Communication2018 IEEE/MTT-S International Microwave Symposium - IMS10.1109/MWSYM.2018.8439430(663-666)Online publication date: Jun-2018

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