Test cost reduction for X-value elimination by scan slice correlation analysis
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- Test cost reduction for X-value elimination by scan slice correlation analysis
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Test Cost Reduction for X-Value Elimination By Scan Slice Correlation Analysis
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)X-values in test output responses corrupt an output response compaction and can cause a fault coverage loss. X-Masking and X-Canceling MISR methods have been suggested to eliminate X-values, however, there are control data volume and test time overhead ...
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03: Proceedings of the 21st IEEE VLSI Test SymposiumIt is common to use ATPG of scan-based design forhigh fault coverage in LSI testing. However, significantincrease in test cost is caused in accordance withincreasing design complexity. Recent strategies for testcost reduction combine ATPG and BIST ...
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A new scan architecture called reconfigured scan forest is proposed for cost-effective scan testing. Multiple scan flip-flops can be grouped based on structural analysis that avoids new untestable faults due to new reconvergent fanouts. The proposed new ...
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- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE Council on Electronic Design Automation (CEDA)
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Association for Computing Machinery
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- National Research Foundation of Korea by the Ministry of Education
- MOTIE (Ministry of Trade, Industry Energy and KSRC(Korea Semiconductor Research Consortium)
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