research-article

HLSPredict: cross platform performance prediction for FPGA high-level synthesis

Authors:

Kenneth O'Neal,

Kennen DeRenard,

Philip BriskAuthors Info & Claims

ICCAD '18: Proceedings of the International Conference on Computer-Aided Design

Article No.: 104, Pages 1 - 8

https://doi.org/10.1145/3240765.3264635

Published: 05 November 2018 Publication History

Abstract

FPGA application developers must explore increasingly large design spaces to identify regions of code to accelerate. High-Level Synthesis (HLS) tools automatically derive FPGA-based designs from high-level language specifications, which improves designer productivity; however, HLS tool run-times are cost-prohibitive for design space exploration, preventing designers from adequately answering cost-value decisions without expert guidance. To address this concern, this paper introduces a machine learning framework to predict FPGA performance and power consumption without relying on analytical models or HLS tools in-the-loop. For workloads that were manually optimized by appropriately setting pragmas, the framework obtains a worst-case relative error of 9.08% while running 43.78x faster than HLS; for unoptimized workloads, the framework obtains a worst-case relative error of 9.79% while running 36.24x faster than HLS.

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Cited By

Jang SCho Y(2024)Reinforcement Learning-Driven Bit-Width Optimization for the High-Level Synthesis of Transformer Designs on Field-Programmable Gate ArraysElectronics10.3390/electronics1303055213:3(552)Online publication date: 30-Jan-2024
https://doi.org/10.3390/electronics13030552
Ferikoglou AKakolyris AMasouros DSoudris DXydis S(2024)CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design OptimizationACM Transactions on Reconfigurable Technology and Systems10.1145/370200518:1(1-32)Online publication date: 26-Oct-2024
https://dl.acm.org/doi/10.1145/3702005
Liu FLi HHu WHe Y(2024)Review of neural network model acceleration techniques based on FPGA platformsNeurocomputing10.1016/j.neucom.2024.128511(128511)Online publication date: Aug-2024
https://doi.org/10.1016/j.neucom.2024.128511
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Index Terms

HLSPredict: cross platform performance prediction for FPGA high-level synthesis
1. Hardware
  1. Electronic design automation

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cover image ACM Other conferences

ICCAD '18: Proceedings of the International Conference on Computer-Aided Design

November 2018

1020 pages

ISBN:9781450359504

DOI:10.1145/3240765

General Chair:
Iris Bahar
Brown Univ. School of Engineering, Providence, RI

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2018

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US National Science Foundation

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ICCAD '18

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IEEE-EDS

ICCAD '18: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN

November 5 - 8, 2018

California, San Diego

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Jang SCho Y(2024)Reinforcement Learning-Driven Bit-Width Optimization for the High-Level Synthesis of Transformer Designs on Field-Programmable Gate ArraysElectronics10.3390/electronics1303055213:3(552)Online publication date: 30-Jan-2024
https://doi.org/10.3390/electronics13030552
Ferikoglou AKakolyris AMasouros DSoudris DXydis S(2024)CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design OptimizationACM Transactions on Reconfigurable Technology and Systems10.1145/370200518:1(1-32)Online publication date: 26-Oct-2024
https://dl.acm.org/doi/10.1145/3702005
Liu FLi HHu WHe Y(2024)Review of neural network model acceleration techniques based on FPGA platformsNeurocomputing10.1016/j.neucom.2024.128511(128511)Online publication date: Aug-2024
https://doi.org/10.1016/j.neucom.2024.128511
Ye HJun HYang JChen DChinnery DHui-Ru Jiang I(2023)High-level Synthesis for Domain Specific ComputingProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3580027(211-219)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3580027
Hwang DYeleuov SSeo JChung MMoon HPaek Y(2023)Ambassy: A Runtime Framework to Delegate Trusted Applications in an ARM/FPGA Hybrid SystemIEEE Transactions on Mobile Computing10.1109/TMC.2021.308614322:2(708-719)Online publication date: 1-Feb-2023
https://doi.org/10.1109/TMC.2021.3086143
Wu NXie YHao C(2023)IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.318554042:3(900-913)Online publication date: Mar-2023
https://doi.org/10.1109/TCAD.2022.3185540
Goswami PBhatia D(2023)Application of Machine Learning in FPGA EDA Tool DevelopmentIEEE Access10.1109/ACCESS.2023.332235811(109564-109580)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3322358
Wu NXie Y(2022)A Survey of Machine Learning for Computer Architecture and SystemsACM Computing Surveys10.1145/349452355:3(1-39)Online publication date: 3-Feb-2022
https://dl.acm.org/doi/10.1145/3494523
Wu NYang HXie YLi PHao COshana R(2022)High-level synthesis performance prediction using GNNsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530408(49-54)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530408
Goswami PShahshahani MBhatia D(2022)MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789084(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789084
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