Article

Free access

A novel high throughput reconfigurable FPGA architecture

Authors:

Luca Macchiarulo,

Arindam Mukherjee,

Malgorzata Marek-SadowskaAuthors Info & Claims

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Pages 22 - 29

https://doi.org/10.1145/329166.329174

Published: 01 February 2000 Publication History

Abstract

With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. This architecture utilizes the concept of 'Wave-Steering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5μ CMOS technology.

References

[1]

V. Bertacco et al, "Decision Diagrams and Pass Transistor Logic Synthesis", Prec. of the ACM/IEEE Int'l Workshop on Logic Synthesis, pp. 1-5, May 1997.

[2]

V. Betz, J. Rose, A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999.

Digital Library

[3]

E. I. Boemo, S. Lopez-Buedo, J. M. Meneses, "Some Experiments About Wave-Pipelining FPGA's", IEEE Trans. On Very Large Scale Integration Systems, Vol.6, No.2, pp. 232-237, June 1998.

Digital Library

[4]

G. Borriello, C. Ebeling, S.A. Hauck, S. Bums, "The Triptych FPGA Architecture", IEEE Transactions on VLSI Systems, Vol.3, No.4, Dee. 1995, pp.491-501.

Digital Library

[5]

R.E. Bryant, "Graph-based Algorithms for Boolean functions manipulation", IEEE Trans. Computers, Vol. C-35, pp. 677-691, Aug. 1986.

Digital Library

[6]

P. Buch et al, "On Synthesizing Pass Transistor Networks", Prec. of the ACM/IEEE Int'l Workshop on Logic Synthesis, pp. 1- 8, May 1997.

[7]

P. Buch, A. Narayan, A.R. Newton, A. Sangiovanni-Vincentelli, "Logic Synthesis for Large Pass Transistor Circuits", ICCAD '97, November 1997.

Digital Library

[8]

W.P. Burleson, M. Ciesielski, E Klass, W. Liu, "Wave-Pipelining:A Tutorial and Research Survey", IEEE Trans. on VLSI Systems, Vol.6, No.3, Sep.'98.

Digital Library

[9]

L,Cotten, "Maximum Rate Pipelined Systems", Prec. AFIPS Spring Joint Comp. Conf., 1969.

[10]

B.V. Herzen, "Signal Processing at 250 MHz Using High-Performance FPGAs", IEEE Trans. on VLSI Systems, Vol. 6. No.2, June '98.

Digital Library

[11]

S.Y. Kung, "VLSI Array Processors", Prentice Hall, 1988.

Digital Library

[12]

W.K.C.Lam, R.K.Brayton and A.L.Sangiovanni-Vincentelli, "Valid Clock Frequencies and Their Computation in Wave pipelined Circuits", IEEE Transactions on CAD of IC and Systems, Vol. 15, No.7, July 1996.

Digital Library

[13]

A. Mukherjee, R. Sudhakar, M.Marek-Sadowska, S.I. Long, "Wave Steering in YADDs: A Novel Non-iterative Synthesis and Layout Technique", Proc. Design Automation Conference '99, pp 466-471.

Digital Library

[14]

A. Mukherjee, M. Marek-Sadowska, S.I. Long,"Wave Pipelining YADDs- A Feasibility Study", Proc, IEEE Custom Integrated Circuits Conference, '99, pp 559-562.

[15]

M. Shamanna, K, Cameron, S.R. Whitaker, "Multiple-input, Multiple-output Pass Transistor Logic", Int'l Journal Electronics, Vol. 79, No. 1, July 1995.

[16]

R.Sudhakar, "YADDA: Layout Synthesis using Pass Transistor Logic", MS Thesis, UCSB, 1998.

[17]

K. Taki, "A Survey for Pass-Transistor Logic Technologies", ASP-DAC, February 1998.

[18]

W. Tsu et al, "HSRA: High Speed, Hierarchical Synchronous Reconfigurable Array", ACM International Symposium on FPGAs, 1999, pp. 125-134.

Digital Library

[19]

K.Yano et al, "A 3.8ns CMOS 1.6xl6b Multiplier using Complementary Pass-Transistor Logic", IEEE J.Solid-State Circuits, Vol.25, no.2, pp.388-395, April, 1990.

[20]

The Programmable Logic Data Book, Xilinx Inc. 1999.

[21]

URL: http://www.xilinx.com/products/logicore/lcoredes.htm

Cited By

Singh AMukherjee AMacchiarulo LMarek-Sadowska M(2003)PITIAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81078011:3(354-363)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.810780
Mal PCantin JBeyette F(2002)The circuit designs of an SRAM based look-up table for high performance FPGA architectureThe 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.10.1109/MWSCAS.2002.1187013(III-227-III-230)Online publication date: 2002
https://doi.org/10.1109/MWSCAS.2002.1187013
Mal PBeyette F(2002)Development of an FPGA for multitechnology applicationsThe 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.10.1109/MWSCAS.2002.1186998(III-172-III-175)Online publication date: 2002
https://doi.org/10.1109/MWSCAS.2002.1186998
Show More Cited By

Index Terms

A novel high throughput reconfigurable FPGA architecture
1. Hardware

Recommendations

High throughput architecture for packet classification using FPGA
ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

To avoid packet classification from being the performance bottleneck in network devices, one-chip solution hardware packet classifier based on HiCuts algorithm is designed and implemented in single chip of FPGA. The compact data structure and the ...
FPGA implementation of AES algorithm for high throughput using folded parallel architecture

This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret ...
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio
ICETC '09: Proceedings of the 2009 International Conference on Education Technology and Computer

Major functions of “Software Defined Radios( SDRs )” are signal processing functions (SPF) and the basic building blocks for most of these functions are multipliers , adders, delays , square roots, trigonometric functions etc.. The SPFs are ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

223 pages

ISBN:1581131933

DOI:10.1145/329166

Chairmen:
Steve Trimberger
Xilinx, San Jose, CA
,
Scott Hauck
Univ. of Washington, Seattle

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 2000

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPGA00

Sponsor:

SIGDA

FPGA00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 10 - 11, 2000

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
656
Total Downloads

Downloads (Last 12 months)59
Downloads (Last 6 weeks)11

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Singh AMukherjee AMacchiarulo LMarek-Sadowska M(2003)PITIAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81078011:3(354-363)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.810780
Mal PCantin JBeyette F(2002)The circuit designs of an SRAM based look-up table for high performance FPGA architectureThe 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.10.1109/MWSCAS.2002.1187013(III-227-III-230)Online publication date: 2002
https://doi.org/10.1109/MWSCAS.2002.1187013
Mal PBeyette F(2002)Development of an FPGA for multitechnology applicationsThe 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.10.1109/MWSCAS.2002.1186998(III-172-III-175)Online publication date: 2002
https://doi.org/10.1109/MWSCAS.2002.1186998
Singh AMukherjee AMarek-Sadowska MRabaey J(2001)Latency and latch count minimization in wave steered circuitsProceedings of the 38th annual Design Automation Conference10.1145/378239.378529(383-388)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378529
Singh AMukherjee AMarek-Sadowska MHauck S(2001)Interconnect pipelining in a throughput-intensive FPGA architectureProceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays10.1145/360276.360323(153-160)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1145/360276.360323

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents