research-article

Public Access

Control Flow Checking or Not? (for Soft Errors)

Authors:

Abhishek Rhisheekesan,

Reiley Jeyapaul,

Aviral ShrivastavaAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 18, Issue 1

Article No.: 11, Pages 1 - 25

https://doi.org/10.1145/3301311

Published: 15 February 2019 Publication History

All formats PDF

Abstract

Huge leaps in performance and power improvements of computing systems are driven by rapid technology scaling, but technology scaling has also rendered computing systems susceptible to soft errors. Among the soft error protection techniques, Control Flow Checking (CFC) based techniques have gained a reputation of being lightweight yet effective. The main idea behind CFCs is to check if the program is executing the instructions in the right order. In order to validate the protection claims of existing CFCs, we develop a systematic and quantitative method to evaluate the protection achieved by CFCs using the metric of vulnerability. Our quantitative analysis indicates that existing CFC techniques are not only ineffective in providing protection from soft faults, but incur additional performance and power overheads. Our results show that software-only CFC protection schemes increase system vulnerability by 18%--21% with 17%--38% performance overhead and hybrid CFC protection increases vulnerability by 5%. Although the vulnerability remains almost the same for hardware-only CFC protection, they incur overheads of design cost, area, and power due to the hardware modifications required for their implementations.

References

[1]

2010. Amber ARM-compatible core :: Overview. http://opencores.org/project,amber.

[2]

Z. Alkhalifa, V. S. S. Nair, N. Krishnamurthy, and J. A. Abraham. 1999. Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans. Parallel Distrib. Syst. 10, 6 (June 1999), 627--641.

Digital Library

[3]

S. A. Asghari, H. Taheri, H. Pedram, and O. Kaynak. 2014. Software-based control flow checking against transient faults in industrial environments. IEEE Trans. Indust. Inf. 10, 1 (Feb. 2014), 481--490.

[4]

J. R. Azambuja, M. Altieri, J. Becker, and F. L. Kastensmidt. 2013. HETA: Hybrid error-detection technique using assertions. IEEE Trans. Nucl. Sci. 60, 4 (Aug. 2013), 2805--2812.

[5]

Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1--7.

Digital Library

[6]

A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan. 2005. Computing architectural vulnerability factors for address-based structures. In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA’05). 532--543.

Digital Library

[7]

Preston Briggs, Keith D. Cooper, Timothy J. Harvey, and L. Taylor Simpson. 1998. Practical improvements to the construction and destruction of static single assignment form. Softw. Pract. Exper. 28, 8 (July 1998), 859--881.

Digital Library

[8]

Wang Chao, Fu Zhongchuan, Chen Hongsong, Ba Wei, Li Bin, Chen Lin, Zhang Zexu, Wang Yuying, and Cui Gang. 2010. CFCSS without aliasing for SPARC architecture. In Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT’10). 2094--2100.

Digital Library

[9]

E. Chielle, G. S. Rodrigues, F. L. Kastensmidt, S. Cuenca-Asensi, L. A. Tambara, P. Rech, and H. Quinn. 2015. S-SETA: Selective software-only error-detection technique using assertions. IEEE Trans. Nucl. Sci. 62, 6 (Dec. 2015), 3088--3095.

[10]

M. Duricek and T. Krajcovic. 2014. Interactive hybrid control-flow checking method. In Proceedings of the 2014 International Conference on Applied Electronics. 79--82.

[11]

J. B. Eifert and J. P. Shen. 1995. Processor monitoring using asynchronous signatured instruction streams. In Proceedings of the 25th International Symposium on Fault-Tolerant Computing, 1995, “Highlights from Twenty-Five Years’.” 106.

[12]

N. Farazmand, M. Fazeli, and S. G. Miremadi. 2008. FEDC: Control flow error detection and correction for embedded systems without program interruption. In Proceedings of the 3rd International Conference on Availability, Reliability and Security (ARES’08). 33--38.

Digital Library

[13]

Xin Fu, Tao Li, and José A. B. Fortes. 2006. Sim-SODA: A unified framework for architectural level software reliability analysis. In Proceedings of the Workshop on Modeling, Benchmarking and Simulation (held in conjunction with International Symposium on Computer Architecture).

[14]

K. T. Gardiner, A. Yakovlev, and A. Bystrov. 2007. A C-element latch scheme with increased transient fault tolerance for asynchronous circuits. In Proceedings of the13th IEEE International On-Line Testing Symposium (IOLTS’07). 223--230.

Digital Library

[15]

O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, and M. Violante. 2003. Soft-error detection using control flow assertions. In Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 581--588.

Digital Library

[16]

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the 2001 IEEE International Workshop on Workload Characterization, WWC-4. (WWC’01). IEEE Computer Society, Washington, DC, 3--14.

Digital Library

[17]

P. Hazucha, T. Karnik, S. Walstra, B. Bloechel, J. Tschanz, J. Maiz, K. Soumyanath, G. Dermer, S. Narendra, V. De, and S. Borkar. 2003. Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. In Proceedings of the IEEE 2003 Custom Integrated Circuits Conference. 617--620.

[18]

J. Hennessy and D. Patterson. 2012. Computer Architecture: A Quantitative Approach (5th ed.). Morgan Kaufmann.

Digital Library

[19]

Intel Corporation. 1997. Pentium Processor Family Developer’s Manual. Intel Corporation.

[20]

R. Jeyapaul, Fei Hong, A. Rhisheekesan, A. Shrivastava, and Kyoungwoo Lee. 2011. UnSync: A soft error resilient redundant multicore architecture. In Proceedings of the International Conference on Parallel Processing (ICPP’11). 632--641.

Digital Library

[21]

Sammy Kayali. 2000. Reliability considerations for advanced microelectronics. In Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC’00). IEEE Computer Society, Washington, DC, 99. http://portal.acm.org/citation.cfm?id=826038.826937

Digital Library

[22]

Chris Lattner and Vikram Adve. 2004. LLVM: A compilation framework for lifelong program analysis and transformation. In Proceedings of the International Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization (CGO’04). IEEE Computer Society, Washington, DC, 75--. http://dl.acm.org/citation.cfm?id=977395.977673

Digital Library

[23]

H. Madeira and J. G. Silva. 1991. On-line signature learning and checking: Experimental evaluation. In CompEuro’91. Proceedings of the 5th Annual European Computer Conference on Advanced Computer Technology, Reliable Systems and Applications.642--646.

[24]

T. Michel, R. Leveugle, and G. Saucier. 1991. A new approach to control flow checking without program modification. In Proceedings of the 21st International Symposium on Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers. 334--341.

[25]

G. Miremadi, J. Ohlsson, M. Rimen, and J. Karlsson. 1998. Use of time, location and instruction signatures for control flow checking. In Proceedings of the DCCA-5 International Conference.

[26]

P. Montesinos, W. Liu, and J. Torrellas. 2006. Shield: Cost-effective soft-error protection for register files. In Proceedings of the 3rd IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC’06).

[27]

Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin. 2003. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. IEEE/ACM International Symposium on Microarchitecture 0 (2003), 29.

Digital Library

[28]

N. Oh, P. P. Shirvani, and E. J. McCluskey. 2002. Control-flow checking by software signatures. IEEE Trans. Reliab. 51, 1 (March 2002), 111--122.

[29]

N. Oh, P. P. Shirvani, and E. J. McCluskey. 2002. Error detection by duplicated instructions in super-scalar processors. IEEE Trans. Reliab. 51, 1 (March 2002), 63--75.

[30]

J. Ohlsson, M. Rimen, and U. Gunneflo. 1992. A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers. 316--325.

[31]

L. Parra, A. Lindoso, M. Portela, L. Entrena, F. Restrepo-Calle, S. Cuenca-Asensi, and A. Marínez-Álvarez. 2013. Efficient mitigation of data and control flow errors in microprocessors. In Proceedings of the 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS’13). 1--4.

[32]

A. Rajabzadeh and S. G. Miremadi. 2006. CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing. Microelectron. Reliab. 46, 5 (2006), 959--972.

[33]

Abhishek Rhisheekesan. 2012. Quantitative Evaluation of Control Flow based Soft Error Protection Mechanisms. Master’s thesis. School of Computing, Informatics and Decision Systems Engineering, Arizona State University.

[34]

N. R. Saxena and W. K. McCluskey. 1990. Control-flow checking using watchdog assists and extended-precision checksums. IEEE Trans. Comput. 39, 4 (April 1990), 554--559.

Digital Library

[35]

Michael A. Schuette and John Paul Shen. 1983. On-line monitoring using signatured instruction streams. In Proceedings of the 13th International Test Conference. 275--282.

[36]

Michael A. Schuette and John Paul Shen. 1987. Processor control flow monitoring using signatured instruction streams. IEEE Trans. Comput. 36, 3 (March 1987), 264--276.

Digital Library

[37]

Jared C. Smolens, Brian T. Gold, Babak Falsafi, and James C. Hoe. 2006. Reunion: Complexity-effective multicore redundancy. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 39). IEEE Computer Society, Washington, DC, 223--234.

Digital Library

[38]

Darshan D. Thaker, Francois Impens, Isaac L. Chuang, Rajeevan Amirtharajah, and Frederic T. Chong. 2008. On Using Recursive TMR as a Soft Error Mitigation Technique. http://citeseerx.ist.psu.edu/viewdoc/download?rep=rep18type=pdf8doi=10.1.1.131.523

[39]

Ramtilak Vemu and Jacob Abraham. 2011. CEDA: Control-flow error detection using assertions. IEEE Trans. Comput. 60, 9 (Sept. 2011), 1233--1245.

Digital Library

[40]

R. Vemu, S. Gurumurthy, and J. A. Abraham. 2007. ACCE: Automatic correction of control-flow errors. In Proceedings of the IEEE International Test Conference (ITC’07). 1--10.

[41]

Rajesh Venkatasubramanian, J. P. Hayes, and B. T. Murray. 2003. Low-cost on-line fault detection using control flow assertions. In Proceedings of the 9th IEEE On-Line Testing Symposium (IOLTS’03). 137--143.

[42]

Kent Wilken and John Paul Shen. 1988. Continuous signature monitoring: Efficient concurrent-detection of processor control errors. In Proceedings of the 1988 International Conference on Test: New Frontiers in Testing (ITC’88). IEEE Computer Society, Washington, DC, 914--925. http://dl.acm.org/citation.cfm?id=1896122.1896279

Digital Library

Cited By

Didehban MSo HGali PShrivastava ALee K(2024)Generic Soft Error Data and Control Flow Error Detection by Instruction DuplicationIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.324584221:1(78-92)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TDSC.2023.3245842
Yan ZZhuang YZhang QGu JGuo L(2023)A configurable control flow error detection method based on basic block repartitionMicroelectronics Reliability10.1016/j.microrel.2023.115070147(115070)Online publication date: Aug-2023
https://doi.org/10.1016/j.microrel.2023.115070
Mishra TChantem TGerdes R(2022)Survey of Control-flow Integrity Techniques for Real-time Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/353827521:4(1-32)Online publication date: 18-Jul-2022
https://dl.acm.org/doi/10.1145/3538275
Show More Cited By

Index Terms

Control Flow Checking or Not? (for Soft Errors)
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Reliability
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures
  2. Software organization and properties
    1. Software system structures
      1. Software architectures
        Data flow architectures

Recommendations

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors
DAC '14: Proceedings of the 51st Annual Design Automation Conference

Control Flow Checking (CFC) based techniques have gained a reputation of providing effective, yet low-overhead protection from soft errors. The basic idea is that if the control flow -- or the sequence of instructions that are executed -- is correct, ...
Protecting Caches from Soft Errors: A Microarchitect’s Perspective
Special Issue on Secure and Fault-Tolerant Embedded Computing and Regular Papers

Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection ...
Root cause analysis of soft-error-induced failures from hardware and software perspectives
Abstract
Because the dangers of soft errors are increasing with continued technology scaling, reliability against soft errors is becoming an important design concern for modern embedded systems. Various schemes have been proposed to protect ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 18, Issue 1

Special Issue on MEMOCODE 2017 and Regular Papers

January 2019

259 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3305158

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

Issue’s Table of Contents

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 15 February 2019

Accepted: 01 November 2018

Revised: 01 November 2018

Received: 01 March 2018

Published in TECS Volume 18, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

National Science Foundation

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

15
Total Citations
View Citations
1,325
Total Downloads

Downloads (Last 12 months)555
Downloads (Last 6 weeks)39

Reflects downloads up to 10 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Didehban MSo HGali PShrivastava ALee K(2024)Generic Soft Error Data and Control Flow Error Detection by Instruction DuplicationIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.324584221:1(78-92)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TDSC.2023.3245842
Yan ZZhuang YZhang QGu JGuo L(2023)A configurable control flow error detection method based on basic block repartitionMicroelectronics Reliability10.1016/j.microrel.2023.115070147(115070)Online publication date: Aug-2023
https://doi.org/10.1016/j.microrel.2023.115070
Mishra TChantem TGerdes R(2022)Survey of Control-flow Integrity Techniques for Real-time Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/353827521:4(1-32)Online publication date: 18-Jul-2022
https://dl.acm.org/doi/10.1145/3538275
Ahmad HSedaghat Y(2022)Software-based Control-Flow Error Detection with Hardware Performance Counters in ARM Processors2022 CPSSI 4th International Symposium on Real-Time and Embedded Systems and Technologies (RTEST)10.1109/RTEST56034.2022.9850096(1-8)Online publication date: 30-May-2022
https://doi.org/10.1109/RTEST56034.2022.9850096
Sharif UMueller-Gritschneder DSchlichtmann U(2022)COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V2022 11th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO55406.2022.9797144(1-4)Online publication date: 7-Jun-2022
https://doi.org/10.1109/MECO55406.2022.9797144
Koylu TFieback MHamdioui STaouil M(2022)Using Hopfield Networks to Correct Instruction Faults2022 IEEE 31st Asian Test Symposium (ATS)10.1109/ATS56056.2022.00030(102-107)Online publication date: Nov-2022
https://doi.org/10.1109/ATS56056.2022.00030
Gava JBandeira VRosa FGaribotti RReis ROst L(2022)SOFIA: An automated framework for early soft error assessment, identification, and mitigationJournal of Systems Architecture10.1016/j.sysarc.2022.102710131(102710)Online publication date: Oct-2022
https://doi.org/10.1016/j.sysarc.2022.102710
Al-haj Ahmad HSedaghat Y(2022)CAFIMicroprocessors & Microsystems10.1016/j.micpro.2022.10464894:COnline publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1016/j.micpro.2022.104648
Sharif UMueller-Gritschneder DSchlichtmann U(2021)REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault ToleranceACM Transactions on Embedded Computing Systems10.1145/347700120:5s(1-22)Online publication date: 23-Sep-2021
https://dl.acm.org/doi/10.1145/3477001
Li SDi SZhao KLiang XChen ZCappello Fde Supinski BHall MGamblin T(2021)Resilient error-bounded lossy compressor for data transferProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3458817.3476195(1-14)Online publication date: 14-Nov-2021
https://dl.acm.org/doi/10.1145/3458817.3476195
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents