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View all- Farah RHarmanani H(2008)An Ant Colony Optimization approach for test pattern generation2008 Canadian Conference on Electrical and Computer Engineering10.1109/CCECE.2008.4564771(001397-001402)Online publication date: May-2008
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
Authors: 
Fulvio Corno, 
Paolo prinetto, Maurizio Rebaudenpgo, 
Matteo Sonza ReordaAuthors Info & Claims
Fulvio Corno, Paolo prinetto, Maurizio Rebaudenpgo, Matteo Sonza ReordaAuthors Info & ClaimsPages 228 - 232
References
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[2]
V.D. Agrawal, K.-T. Cheng, P. Agrawal, "CONTEST: A Concurrent Test Generator for Sequential Circuits," Proc. 25th Design Automation Conference, 1988. pp. 84-89
[3]
F. Brglez, D. Bryant, K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. Int. Syrup. on Circ'. And Systems, t 989, pp. 1929-1934
[4]
P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda, "A simulation-based approach to test pattern generation for synchronous circuits," Proc. IEEE VLS! Test Sy, wwslum, 1992, pp. 263-267
[5]
H. Cho, G.D. Hatchel, F. Somenzi, "Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration," IEEE Trans. on CAD/ICAS, Vot. CAD-12, No. 7, pp. 935- 945, 1993
[6]
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca, "Advanced Techniques for GA-based sequential ATPGs," IEEE European Design and Test Conference, 1996, pp. 375-379
[7]
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, "Comparing topological, symbolic and GA-based ATPGs: an experimental approach," IEEE Int. Test Conf., Washington (USA), October 1996, pp. 39-47
[8]
J.H. Holland, "Adaption in Natural and Artificial Systems,'' University of Michigan Press, Ann Arbor (USA), 1975
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S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, "Optimization by simulated annealing," Science, 220, pp. 671-680, 1983
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N. Metropolis, A.W. Rosenbluth, M.N. Rosenbluth, A.H. Teller, E. Teller, "Equation of State Calculations by Fast Computing Machines", J. of Chem. Phys., Vol. 21, No. 6, pp. 1087-1092, 1953
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T. Niermann, J.H. Patel, "HiTEC: A Test Generator Package for Sequential Circuits," Proc. European Design/utomation Conf., 1991, pp. 214-218
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T.M. Niermann, W,-T. Cheng, J.H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator,'' IEEE Trans. on CAD/ICAS, Vol. i 1, No. 2, pp. 198-207, 1992
[14]
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits, IEEE Trans. on CAD/ICAS, V ol. 15, No. 8, pp. 991-1000, 1996
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E.M. Rudnick, J.G. Holm, D.G. Saab, J.H. Patel, "Application of Simple Genetic Algorithms to Sequential Circuit Test Generation," Proc. European Design & Test Conf., 1994, pp. 40-45
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E.M. Rudnick, J.H. Patel, G.S. Greenstein, T.M. Niermann, "Sequential Circuit Test Generation in a Genetic Algorithm Framework," Proc. Design Automation Conf., t994, pp. 698-704
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D.G. Saab, Y.G. Saab, J.A. Abraham, *'CRIS: A Test Cultivation Program for Sequential VLSI Circuits," Proc. !nr Conf on Computer Aided Design, 1992, pp. 216-219
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P. van Laarhoven, E. Aarts, "Simulated Annealing: Theory and Applications", D. Reidel Publishing Co., 1987
Index Terms
- SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
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April 1997
545 pages
ISBN:0897918509
DOI:10.1145/331697
Copyright © 1997 ACM.
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Published: 01 April 1997
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View all- Farah RHarmanani H(2008)An Ant Colony Optimization approach for test pattern generation2008 Canadian Conference on Electrical and Computer Engineering10.1109/CCECE.2008.4564771(001397-001402)Online publication date: May-2008
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