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Simplifying Transactional Memory Support in C++

Authors:

Pantea Zardoshti,

Pavithra Balaji,

Michael L. Scott,

Michael SpearAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 16, Issue 3

Article No.: 25, Pages 1 - 24

https://doi.org/10.1145/3328796

Published: 25 July 2019 Publication History

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Abstract

C++ has supported a provisional version of Transactional Memory (TM) since 2015, via a technical specification. However, TM has not seen widespread adoption, and compiler vendors have been slow to implement the technical specification. We conjecture that the proposed TM support is too difficult for programmers to use, too complex for compiler designers to implement and verify, and not industry-proven enough to justify final standardization in its current form.

To address these problems, we present a different design for supporting TM in C++. By forbidding explicit self-abort, and by introducing an executor-based mechanism for running transactions, our approach makes it easier for developers to get code up and running with TM. Our proposal should also be appealing to compiler developers, as it allows a spectrum of levels of support for TM, with varying performance, and varying reliance on hardware TM support in order to provide scalability.

<?tight?>While our design does not enable some of the optimizations admitted by the current technical specification, we show that it enables the implementation of robust support for TM in a small, orthogonal compiler extension. Our implementation is able to handle a wide range of transactional programs, delivering low instrumentation overhead and scalability and performance on par with the current state of the art. Based on this experience, we believe our approach to be a viable means of reinvigorating the standardization of TM in C++.

References

[1]

Ali-Reza Adl-Tabatabai, Brian T. Lewis, Vijay Menon, Brian R. Murphy, Bratin Saha, and Tatiana Shpeisman. 2006. Compiler and runtime support for efficient software transactional memory. In Proceedings of the 27th ACM Conference on Programming Language Design and Implementation.

Digital Library

[2]

Sara Baghsorkhi and Christos Margiolas. 2018. Automating efficient variable-grained resiliency for low-power IoT systems. In Proceedings of the 2018 International Symposium on Code Generation and Optimization.

Digital Library

[3]

Colin Blundell, E. Christopher Lewis, and Milo M. K. Martin. 2006. Subtleties of transactional memory atomicity semantics. Computer Architecture Letters 5, 2 (Nov. 2006), 17:1–17:4.

Digital Library

[4]

Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. 2007. Performance pathologies in hardware transactional memory. In Proceedings of the 34th International Symposium on Computer Architecture.

Digital Library

[5]

Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, and Maurice Herlihy. 2014. Invyswell: A hybrid transactional memory for Haswell’s restricted transactional memory. In Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques.

Digital Library

[6]

Brian D. Carlstrom, Austen McDonald, Hassan Chafi, JaeWoong Chung, Chi Cao Minh, Christos Kozyrakis, and Kunle Olukotun. 2006. The atomos transactional programming language. In Proceedings of the 27th ACM Conference on Programming Language Design and Implementation.

Digital Library

[7]

Keith Chapman, Antony Hosking, and Eliot Moss. 2016. Hybrid STM/HTM for nested transactions on OpenJDK. In Proceedings of the 31rd ACM Conference on Object Oriented Programming, Systems, Languages, and Applications.

Digital Library

[8]

Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, and Etienne Riviere. 2010. Evaluation of AMD’s advanced synchronization facility within a complete transactional memory stack. In Proceedings of the EuroSys 2010 Conference.

Digital Library

[9]

Luke Dalessandro, Francois Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, and Michael Spear. 2011. Hybrid NOrec: A case study in the effectiveness of best effort hardware transactional memory. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[10]

Luke Dalessandro, Dave Dice, Michael L. Scott, Nir Shavit, and Michael Spear. 2010. Transactional mutex locks. In Proceedings of the Euro-Par 2010 Conference.

Digital Library

[11]

Luke Dalessandro, Michael L. Scott, and Michael Spear. 2010. Transactions as the Foundation of a Memory Consistency Model. In Proceedings of the 24th International Symposium on Distributed Computing.

Digital Library

[12]

Luke Dalessandro, Michael Spear, and Michael L. Scott. 2010. NOrec: Streamlining STM by abolishing ownership records. In Proceedings of the 15th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[13]

Joel Denny, Seyong Lee, and Jeffrey Vetter. 2016. ANVL-C: Static analysis techniques for efficient, correct programming of non-volatile main memory systems. In Proceedings of the 25th ACM International Symposium on High-Performance Parallel and Distributed Computing.

Digital Library

[14]

Dave Dice, Ori Shalev, and Nir Shavit. 2006. Transactional locking II. In Proceedings of the 20th International Symposium on Distributed Computing.

Digital Library

[15]

Pascal Felber, Christof Fetzer, and Torvald Riegel. 2008. Dynamic performance tuning of word-based software transactional memory. In Proceedings of the 13th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[16]

Free Software Foundation. 2012. Transactional Memory in GCC. Retrieved from http://gcc.gnu.org/wiki/TransactionalMemory.

[17]

Tim Harris, Mark Plesko, Avraham Shinar, and David Tarditi. 2006. Optimizing memory transactions. In Proceedings of the 27th ACM Conference on Programming Language Design and Implementation.

Digital Library

[18]

Maurice P. Herlihy and J. Eliot B. Moss. 1993. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th International Symposium on Computer Architecture.

Digital Library

[19]

ISO/IEC JTC 1/SC 22/WG 21. 2015. Technical Specification for C++ Extensions for Transactional Memory. Retrieved from http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4514.pdf.

[20]

Matthew Kilgore, Stephen Louie, Chao Wang, Tingzhe Zhou, Wenjia Ruan, Yujie Liu, and Michael Spear. 2015. Transactional tools for the third decade. In Proceedings of the 10th ACM SIGPLAN Workshop on Transactional Computing.

[21]

Guy Korland, Nir Shavit, and Pascal Felber. 2010. Noninvasive concurrency with Java STM. In Proceedings of the 3rd Workshop on Programmability Issues for Multi-Core Computers.

[22]

Chris Lattner and Vikram Adve. 2004. LLVM: A compilation framework for lifelong program analysis 8 transformation. In Proceedings of the International Symposium on Code Generation and Optimization.

Digital Library

[23]

Heiner Litz, Ricardo Dias, and David Cheriton. 2015. Efficient correction of anomalies in snapshot isolation transactions. ACM Transactions on Architecture and Code Optimization 11, 4 (Dec. 2015), 65:1--65:24.

Digital Library

[24]

Yujie Liu, Justin Gottschlich, Gilles Pokam, and Michael Spear. 2015. TSXProf: Profiling hardware transactions. In Proceedings of the 24th International Conference on Parallel Architectures and Compilation Techniques. San Francisco, CA.

Digital Library

[25]

José F. Martínez and Josep Torrellas. 2002. Speculative synchronization: Applying thread-level speculation to explicitly parallel applications. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[26]

Alexander Matveev and Nir Shavit. 2015. Reduced hardware NORec: A safe and scalable hybrid transactional memory. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[27]

Vijay Menon, Steven Balensiefer, Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Richard Hudson, Bratin Saha, and Adam Welc. 2008. Practical weak-atomicity semantics for Java STM. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[28]

Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, and Kunle Olukotun. 2008. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the IEEE International Symposium on Workload Characterization.

[29]

Takuya Nakaike, Rei Odaira, Matthew Gaudet, Maged M. Michael, and Hisanobu Tomari. 2015. Quantitative comparison of hardware transactional memory for blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8. In Proceedings of the 42nd Annual International Symposium on Computer Architecture. Portland, OR.

Digital Library

[30]

Yang Ni, Adam Welc, Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Cownie, Robert Geva, Sergey Kozhukow, Ravi Narayanaswamy, Jeffrey Olivier, Serguei Preis, Bratin Saha, Ady Tal, and Xinmin Tian. 2008. Design and implementation of transactional constructs for C/C++. In Proceedings of the 23rd ACM Conference on Object Oriented Programming, Systems, Languages, and Applications.

Digital Library

[31]

Victor Pankratius and Ali-Reza Adl-Tabatabai. 2011. A study of transactional memory vs. locks in practice. In Proceedings of the 23rd ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[32]

Ravi Rajwar and James R. Goodman. 2001. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th IEEE/ACM International Symposium on Microarchitecture.

Digital Library

[33]

Ravi Rajwar and James R. Goodman. 2002. Transactional lock-free execution of lock-based programs. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[34]

Wenjia Ruan and Michael Spear. 2015. Hybrid transactional memory revisited. In Proceedings of the 29th International Symposium on Distributed Computing.

Digital Library

[35]

Wenjia Ruan, Trilok Vyas, Yujie Liu, and Michael Spear. 2014. Transactionalizing legacy code: An experience report using GCC and memcached. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems.

Digital Library

[36]

Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh, and Benjamin Hertzberg. 2006. McRT-STM: A high performance software transactional memory system for a multi-core runtime. In Proceedings of the 11th ACM Symposium on Principles and Practice of Parallel Programming. New York, NY.

Digital Library

[37]

William N. Scherer III and Michael L. Scott. 2005. Advanced contention management for dynamic software transactional memory. In Proceedings of the 24th ACM Symposium on Principles of Distributed Computing.

Digital Library

[38]

Nir Shavit and Dan Touitou. 1995. Software transactional memory. In Proceedings of the 14th ACM Symposium on Principles of Distributed Computing.

Digital Library

[39]

Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Robert Geva, Yang Ni, and Adam Welc. 2009. Towards transactional memory semantics for C++. In Proceedings of the 21st ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[40]

Michael Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott. 2008. Ordering-based semantics for software transactional memory. In Proceedings of the 12th International Conference on Principles of DIstributed Systems.

Digital Library

[41]

Michael Spear, Michael Silverman, Luke Dalessandro, Maged M. Michael, and Michael L. Scott. 2008. Implementing and exploiting inevitability in software transactional memory. In Proceedings of the 37th International Conference on Parallel Processing.

Digital Library

[42]

Bjarne Stroustrup. 2012. Foundations of C++ (keynote lecture). In Proceedings of the European Joint Conference on Theory and Practice of Software.

[43]

Takayuki Usui, Yannis Smaragdakis, Reimer Behrends, and Jacob Evans. 2009. Adaptive locks: Combining transactions and locks for efficient concurrency. In Proceedings of the 18th International Conference on Parallel Architecture and Compilation Techniques.

Digital Library

[44]

Adam Welc, Bratin Saha, and Ali-Reza Adl-Tabatabai. 2008. Irrevocable transactions and their applications. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures. Munich, Germany.

Digital Library

[45]

Richard Yoo, Christopher Hughes, Konrad Lai, and Ravi Rajwar. 2013. Performance evaluation of Intel transactional synchronization extensions for high performance computing. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis.

Digital Library

[46]

Richard Yoo, Yang Ni, Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai, and Hsien-Hsin Lee. 2008. Kicking the tires of software transactional memory: Why the going gets tough. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[47]

Tingzhe Zhou, Pantea Zardoshti, and Michael Spear. 2017. Practical experience with transactional lock elision. In Proceedings of the 46th International Conference on Parallel Processing.

Cited By

Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Dalvandi SDongol B(2022)Implementing and verifying release-acquire transactional memory in C11Proceedings of the ACM on Programming Languages10.1145/35633526:OOPSLA2(1817-1844)Online publication date: 31-Oct-2022
https://dl.acm.org/doi/10.1145/3563352
Honorio BDe Carvalho JMorales CBaldassin AAraujo G(2022)Using Barrier Elision to Improve Transactional Code GenerationACM Transactions on Architecture and Code Optimization10.1145/353331819:3(1-23)Online publication date: 6-Jul-2022
https://dl.acm.org/doi/10.1145/3533318
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Index Terms

Simplifying Transactional Memory Support in C++
1. Computing methodologies
  1. Concurrent computing methodologies
    1. Concurrent programming languages
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Runtime environments
    2. General programming languages
      1. Language features
        Concurrent programming structures

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 16, Issue 3

September 2019

347 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3341169

Editor:
Koen De Bosschere
Ghent University, Belgium

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Copyright © 2019 ACM.

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Association for Computing Machinery

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Publication History

Published: 25 July 2019

Accepted: 01 April 2019

Revised: 01 March 2019

Received: 01 November 2018

Published in TACO Volume 16, Issue 3

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Cited By

Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Dalvandi SDongol B(2022)Implementing and verifying release-acquire transactional memory in C11Proceedings of the ACM on Programming Languages10.1145/35633526:OOPSLA2(1817-1844)Online publication date: 31-Oct-2022
https://dl.acm.org/doi/10.1145/3563352
Honorio BDe Carvalho JMorales CBaldassin AAraujo G(2022)Using Barrier Elision to Improve Transactional Code GenerationACM Transactions on Architecture and Code Optimization10.1145/353331819:3(1-23)Online publication date: 6-Jul-2022
https://dl.acm.org/doi/10.1145/3533318
D. Jardim AOliveira KJ. Cardoso DDi Domenico DR. Du Bois AH. Cavalheiro G(2021)An extension for Transactional Memory in OpenMPProceedings of the 25th Brazilian Symposium on Programming Languages10.1145/3475061.3475089(58-65)Online publication date: 27-Sep-2021
https://dl.acm.org/doi/10.1145/3475061.3475089
Sheng YHassan ASpear MAgrawal KAzar Y(2021)Semantic Conflict Detection for Transactional Data Structure LibrariesProceedings of the 33rd ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3409964.3461826(446-448)Online publication date: 6-Jul-2021
https://doi.org/10.1145/3409964.3461826
Singh ADave SZardoshti PBrotzman RZhang CGuo XShrivastava ATan GSpear M(2020)SPX64ACM Transactions on Architecture and Code Optimization10.1145/343673018:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3436730
de Carvalho JHonorio BBaldassin AAraujo G(2020)Improving Transactional Code Generation via Variable Annotation and Barrier Elision2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00107(1008-1017)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00107
Zardoshti PSpear MVosoughi ASwart G(2020)Understanding and Improving Persistent Transactions on Optane™ DC Memory2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00044(348-357)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00044
Wu ZLu KWang RZhang W(2020)A survey on optimizations towards best-effort hardware transactional memoryCCF Transactions on High Performance Computing10.1007/s42514-020-00049-2Online publication date: 15-Sep-2020
https://doi.org/10.1007/s42514-020-00049-2
Zardoshti PZhou TLiu YSpear M(2019)Optimizing Persistent Memory Transactions2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT.2019.00025(219-231)Online publication date: Sep-2019
https://doi.org/10.1109/PACT.2019.00025

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