research-article

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs

Authors:

Pierre-Emmanuel GaillardonAuthors Info & Claims

ISPD '21: Proceedings of the 2021 International Symposium on Physical Design

Pages 135 - 142

https://doi.org/10.1145/3439706.3447047

Published: 21 March 2021 Publication History

Abstract

Physical design for Field Programmable Gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device.

References

[1]

Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, B. Xiao, and J. Cong. Optimizing fpga-based accelerator design for deep convolutional neural networks. In FPGA '15, 2015.

Digital Library

[2]

Stephen M. Trimberger. Three ages of FPGAs: A retrospective on the first thirty years of FPGA technology. Proceedings of the IEEE, 103(3):318--331, mar 2015.

[3]

Chaofan Yu, Lingli Wang, and Xuegong Zhou. Automatic layout generator for embedded FPGA cores. In Proceedings of International Conference on ASIC, pages 385--388, 2011.

[4]

Hao Jun Liu. Archipelago-An Open Source FPGA with Toolflow Support. Technical report, 2014.

[5]

B. Neumann, T. Von Sydow, H. Blume, and T. G. Noll. Design flow for embedded FPGAs based on a flexible architecture template. Proceedings -Design, Automation and Test in Europe, DATE, pages 56--61, 2008.

Digital Library

[6]

Ang Li and David Wentzlaff. Cycle-Free FPGA Routing Graphs. In The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 322--322, New York, NY, USA, feb 2020. ACM.

[7]

Xifan Tang, Edouard Giacomin, Aurelien Alacchi, Baudouin Chauviere, and Pierre Emmanuel Gaillardon. OpenFPGA: An opensource framework enabling rapid prototyping of customizable FPGAs. Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, pages 367--374, 2019.

[8]

Xifan Tang, Edouard Giacomin, Baudouin Chauviere, Aurelien Alacchi, and Pierre Emmanuel Gaillardon. OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. IEEE Micro, 40(4):41--48, 2020.

Digital Library

[9]

Jin Hee Kim and Jason H. Anderson. Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2015.

[10]

Ian Kuon, Aaron Egier, and Jonathan Rose. Design, layout and verification of an FPGA using automated tools. In Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05, page 215, New York, New York, USA, 2005. ACM Press.

Digital Library

[11]

Aaron Charles Egier. Enhancing and Using an Automatic Design System for by Copyright c 2005 by Aaron Charles Egier. Master Thesis, 2005.

[12]

Husain Parvez, Hayder Mrabet, and Habib Mehrez. Generic techniques and CAD tools for automated generation of FPGA layout. In PRIME - 2008 PhD Research in Microelectronics and Electronics, Proceedings, pages 141--144, 2008.

[13]

Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, and Jean-Luc Danger. An 8x8 Run-Time Reconfigurable FPGA Embedded in a SoC. In Proceedings of the 45th annual conference on Design automation - DAC '08, New York, New York, USA, 2008. ACM Press.

[14]

Prashanth Mohan, Oguz Atli, Onur Kibar, and Ken Mai. A top-down design methodology for synthesizing fpga fabrics using standard asic flow. pages 313-- 313, 02 2020.

[15]

Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Anderson, Jonathan Rose, and Vaughn Betz. Vtr 7.0: Next generation architecture and cad system for fpgas. ACM Trans. Reconfigurable Technol. Syst., 7(2), July 2014.

[16]

Yanling Zhou, Yunyao Yan, andWei Yan. A method to speed up VLSI hierarchical physical design in floorplanning. In Proceedings of International Conference on ASIC, volume 2017-October, pages 347--350. IEEE Computer Society, jul 2017.

[17]

Jin Hee Kim and Jason H. Anderson. Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. ACM Transactions on Reconfigurable Technology and Systems, 10(2):1--23, apr 2017.

Digital Library

[18]

Weiping Shi and Zhuo Li. A fast algorithm for optimal buffer insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6):879-- 891, 2005.

Digital Library

[19]

David Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Chris Lane, Andy Lee, and Philip Pan. Architectural enhancements in stratix-iii" and stratix-iv". In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '09, page 33--42, New York, NY, USA, 2009. Association for Computing Machinery.

Digital Library

[20]

K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. Titan: Enabling large and complex benchmarks in academic cad. In 2013 23rd International Conference on Field programmable Logic and Applications, pages 1--8, 2013.

Cited By

Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Semi-custom EDAFPGA EDA10.1007/978-981-99-7755-0_7(85-109)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_7
Bhandari JMoosa ATan BPilato CGore GTang XTemple SGaillardon PKarri R(2023)Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP RedactionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330133431:10(1459-1471)Online publication date: Oct-2023
https://doi.org/10.1109/TVLSI.2023.3301334
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Show More Cited By

Index Terms

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs
1. Hardware
  1. Electronic design automation
  2. Very large scale integration design
    1. Standard cell libraries

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Published In

cover image ACM Conferences

ISPD '21: Proceedings of the 2021 International Symposium on Physical Design

March 2021

159 pages

ISBN:9781450383004

DOI:10.1145/3439706

General Chair:
Jens Lienig
Dresden University of Technology, Germany
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Stephen Yang
USA

Copyright © 2021 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 21 March 2021

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Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA)

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ISPD '21

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ISPD '21: International Symposium on Physical Design

March 22 - 24, 2021

Virtual Event, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

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sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Semi-custom EDAFPGA EDA10.1007/978-981-99-7755-0_7(85-109)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_7
Bhandari JMoosa ATan BPilato CGore GTang XTemple SGaillardon PKarri R(2023)Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP RedactionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330133431:10(1459-1471)Online publication date: Oct-2023
https://doi.org/10.1109/TVLSI.2023.3301334
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Neto WLi YGaillardon PYu C(2023)FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed BanditIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321361142:6(1912-1925)Online publication date: Jun-2023
https://doi.org/10.1109/TCAD.2022.3213611
Bhandari JThalakkattu Moosa ATan BPilato CGore GTang XTemple SGaillardon PKarri R(2021)Exploring eFPGA-based Redaction for IP Protection2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643548(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643548

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