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RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA
Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded ...
Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between Accelerators
Graphic processing units (GPUs) are often equipped with HPC systems as accelerators because of their high computing capability. GPUs are powerful computing devices; however, they operate inefficiently on applications that employ partially poor ...
Verifying Hardware Optimizations for Efficient Acceleration
Verifying the correctness of optimizations is a key challenge in hardware acceleration. Incorrect optimizations can produce designs unfit for purpose. This paper presents a novel approach, Covoh, which captures families of hardware designs as ...
Accelerating Decision Tree Ensemble with Guided Branch Approximation
Processing lightweight machine learning (ML) algorithms, such as decision tree ensemble (DTE), on low-power edge devices is beneficial; however, these devices usually have limited resources, and domain-specific accelerators are not readily available. ...
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
The novel communication 6G requires raw data rates of up to 400 Gbit s− 1 in a single Field Programmable Gate Array (FPGA) front-end. For these high data rates, a Software Defined Radio (SDR) on a multi-core processor reaches a performance limit due to ...
Meta-Programming Design-Flow Patterns for Automating Reusable Optimisations
Continuing advances in heterogeneous and parallel computing enable massive performance gains in domains such as AI and HPC. Such gains often involve using hardware accelerators, such as FPGAs and GPUs, to speed up specific workloads. However, to make ...
A single-source C++20 HLS flow for function evaluation on FPGA and beyond.
This paper presents a framework to reuse the intelligence of RTL generators in a single-source HLS setting. This framework is illustrated by a C++ fixed-point library to generate mathematical function evaluator. A compiler flow from C++20 to Vivado IPs ...
Memory and Energy Efficient Memory Model and Instruction Set Architectures for Tree Data Structures
In general, data structures incorporating significant numbers of memory address pointers needlessly occupy large areas of dynamic memory. Moreover, packed binary data structures suffer from slow access time caused by unpacking and repacking. To address ...
Stream Computation of 3D Approximate Convex Hulls with an FPGA
- Tatsuma Mori,
- Daiki Furukawa,
- Keigo Motoyoshi,
- Haruto Ikehara,
- Kaito Ohira,
- Taito Manabe,
- Yuichiro Shibata,
- Tomohiro Ueno,
- Kentaro Sano
The convex hull is the minimum convex set which encloses a given point set. A problem to find convex hulls is not only one of the most fundamental algorithms in computer geometry, but also has a wide variety of practical applications such as robotics ...
Hash Distributed A* on an FPGA
Shortest path problem is a problem of finding a path that minimizes the cost of connecting two nodes in a weighted graph. A* algorithm for solving shortest path search has been applied in various fields such as path navigation systems, automatic robot ...
Non-deterministic event brokered computing
- Andrew Brown,
- Tim Todman,
- Wayne Luk,
- David Thomas,
- Mark Vousden,
- Graeme Bragg,
- Jonny Beaumont,
- Simon Moore,
- Alex Yakovlev,
- Ashur Rafiev
This paper reviews the massively micro-parallel compute system POETS (Partially Ordered Event Triggered System) and illustrates its potential for speeding up demanding applications. Application domains that benefit from POETS include simulations of ...
A Novel Scalable Decision Tree Implementation on SoC Based FPGAs
Machine learning algorithms are rapidly growing in predictive maintenance and condition monitoring systems for valuable assets. Decision tree classification (DTC) is one of popular methods in condition monitoring systems based on vibration analysis. Due ...
Low-power option Greeks: Efficiency-driven market risk analysis using FPGAs
Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these ...
Very Low Power High-Frequency Floating Point FPGA PID Controller
In this work, we present the design and implementation of a floating-point Proportional-Integral-Derivative (PID) controller accelerator which achieves a high rate of 637 K samples per second at 20 mW of power consumption, implemented on a Lattice UP5K ...
Object Detection and Tracking using CouNT and Motion Vectors on FPGA
In this research, we propose a method to accelerate the object detection and tracking using CouNT and motions vectors in compressed video. In our system, first, one frame in a compressed video is decoded, and objects in the frame are detected using ...
Artificial Resilience in neuromorphic systems
Biological beings are intrinsically resilient. This means that they are able to continue to perform a task even if they are partially damaged or if some parts of them don’t work as expected. This is true also for the human brain. The research in these ...
Index Terms
- Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies