research-article

Open access

Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation

Authors:

Wenjian YuAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 339 - 345

https://doi.org/10.1145/3566097.3567882

Published: 31 January 2023 Publication History

Abstract

A series of fixed-structure sparse linear equations are solved in a circuit simulation process. We propose a parallel incomplete LU (ILU) preconditioned GMRES solver for those equations. A new subtree-based scheduling algorithm for ILU factorization and forward/backward substitution is adopted to overcome the load-balancing and data locality problem of the conventional levelization-based scheduling. Experimental results show that the proposed scheduling algorithm can achieve up to 2.6X speedup for ILU factorization and 3.1X speedup for forward/backward substitution compared to the levelization-based scheduling. The proposed ILU-GMRES solver achieves around 4X parallel speedup with 8 threads, which is up to 2.1X faster than that based on the levelization-based scheme. The proposed parallel solver also shows remarkable advantage over existing methods (including HSPICE) on transient simulation of linear and nonlinear circuits.

References

[1]

R. Akhunov, S. Kuksenko, V. Salov, and T. Gazizov. Optimization of the ILU(0) factorization algorithm with the use of compressed sparse row format. Journal of Mathematical Sciences, 191(1):19--27, 2013.

[2]

E. Anderson and Y. Saad. Solving sparse triangular linear systems on parallel computers. International Journal of High Speed Computing, 1(01):73--95, 1989.

Digital Library

[3]

M. Benzi, W. Joubert, et al. Numerical experiments with parallel orderings for ILU preconditioners. Electronic Trans. Numeric Analysis, 8:88--114, 1999.

[4]

L. Blackford, A. Petitet, et al. An updated set of basic linear algebra subprograms (BLAS). ACM Trans.s on Mathematical Software, 28(2):135--151, 2002.

[5]

X. Chen, Y. Wang, and H. Yang. NICSLU: An adaptive sparse matrix solver for parallel circuit simulation. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 32(2):261--274, 2013.

Digital Library

[6]

X. Chen, Y. Wang, and H. Yang. Parallel Sparse Direct Solver for Integrated Circuit Simulation. Springer, 2017.

[7]

E. Chow and A. Patel. Fine-grained parallel incomplete LU factorization. SIAM J. Scientific Comput., 37(2):C169--C193, 2015.

Digital Library

[8]

T. Davis and Y. Hu. The University of Florida sparse matrix collection. ACM Trans. Math. Softw., 38(1):1--25, 2011.

Digital Library

[9]

T. A. Davis and E. Palamadai Natarajan. Algorithm 907: KLU, A Direct Sparse Solver for Circuit Simulation Problems. ACM Trans. Math. Softw., sep 2010.

[10]

L. Dutto and W. Habashi. Parallelization of the ILU(0) preconditioner for CFD problems on shared-memory computers. International J. numerical methods in fluids, 30(8):995--1008, 1999.

[11]

J. Gilbert and J. Liu. Elimination structures for unsymmetric sparse LU factors. SIAM J. Matrix Analysis and Applications, 14(2):334--352, 1993.

Digital Library

[12]

M. Heroux, P. Vu, and C. Yang. A parallel preconditioned conjugate gradient package for solving sparse linear systems on a Cray Y-MP. Applied Numerical Mathematics, 8(2):93--115, 1991.

Digital Library

[13]

D. Hysom and A. Pothen. Efficient parallel computation of ilu (k) preconditioners. In Proc. ACM/IEEE conference on Supercomputing, pages 29--es, 1999.

[14]

D. Hysom and A. Pothen. A scalable parallel algorithm for incomplete factor preconditioning. SIAM J. Scientific Comput., 22(6):2194--2215, 2001.

Digital Library

[15]

Intel Corporation. Developer Reference for Intel® oneAPI Math Kernel Library - C. https://www.intel.com/content/www/us/en/develop/documentation/onemkl-developer-reference-c/top.html, 2022.

[16]

G. Karypis and V. Kumar. A fast and high quality multilevel scheme for partitioning irregular graphs. SIAM J. Scientific Comput., 20(1):359--392, 1998.

Digital Library

[17]

S. Nassif. IBM power grid benchmarks. https://web.ece.ucsb.edu/~lip/PGBenchmarks/ibmpgbench.html, 2008.

[18]

Ngspice. Open source spice simulator. http://ngspice.sourceforge.net/, 2022.

[19]

Y. Saad. ILUT: A dual threshold incomplete LU factorization. Numerical linear algebra with applications, 1(4):387--402, 1994.

[20]

Y. Saad and M. Schultz. GMRES: A generalized minimal residual algorithm for solving nonsymmetric linear systems. SIAM J. Scientific and Statistical Computing, 7(3):856--869, 1986.

[21]

K. Shen, X. Jiao, and T. Yang. Elimination forest guided 2D sparse LU factorization. In Proc. ACM SPAA, pages 5--15, 1998.

Digital Library

[22]

Synopsys, Inc. PrimeSim HSPICE. https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html, 2022.

[23]

H. Thornquist, E. Keiter, R. Hoekstra, D. Day, and E. Boman. A parallel preconditioning strategy for efficient transistor-level circuit simulation. In Proc. ICCAD, pages 410--417, 2009.

Digital Library

[24]

A. Vladimirescu. The SPICE Book. Wiley New York, 1994.

Digital Library

[25]

X. Xu. OpenMP parallel implementation of stiffly stable time-stepping projection/GMRES(ILU(0)) implicit simulation of incompressible fluid flows on shared-memory, multicore architecture. Applied Mathematics and Computation, 355:238--252, 2019.

Digital Library

[26]

J. Zhao, Y. Wen, et al. SFLU: Synchronization-free sparse LU factorization for fast circuit simulation on GPUs. In Proc. ACM/IEEE DAC, pages 37--42, 2021.

Digital Library

[27]

X. Zhao and Z. Feng. GPSCP: A general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations. In Proc. IEEE/ACM ICCAD, pages 429--435, 2012.

Digital Library

Cited By

陈炳(2024)Improved Bordered Block Diagonal Method for Solving Circuit Equation SystemsOperations Research and Fuzziology10.12677/orf.2024.14324914:03(102-108)Online publication date: 2024
https://doi.org/10.12677/orf.2024.143249
Jin ZLi WBai YWang TLu YLiu WKim T(2024)Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper)Proceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473846(96-101)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473846

Index Terms

Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation

Index terms have been assigned to the content through auto-classification.

Recommendations

Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

A number of sparse linear systems are solved by sparse LU factorization in a circuit simulation process. The coefficient matrices of these linear systems have the identical structure but different values. Pivoting is usually needed in sparse LU ...
A Multilevel Dual Reordering Strategy for Robust Incomplete LU Factorization of Indefinite Matrices

A dual reordering strategy based on both threshold and graph reorderings is introduced to construct robust incomplete LU (ILU) factorization of indefinite matrices. The ILU matrix is constructed as a preconditioner for the original matrix to be used in ...
Parallel iterative solvers for sparse linear systems in circuit simulation

For the solution of sparse linear systems from circuit simulation whose coefficient matrices include a few dense rows and columns, a parallel iterative algorithm with distributed Schur complement preconditioning is presented. The parallel efficiency of ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 Owner/Author.

This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IPSJ
IEEE CAS
IEEE CEDA
IEICE

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 January 2023

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Conference

ASPDAC '23

Sponsor:

SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

Acceptance Rates

ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
308
Total Downloads

Downloads (Last 12 months)183
Downloads (Last 6 weeks)30

Reflects downloads up to 22 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

陈炳(2024)Improved Bordered Block Diagonal Method for Solving Circuit Equation SystemsOperations Research and Fuzziology10.12677/orf.2024.14324914:03(102-108)Online publication date: 2024
https://doi.org/10.12677/orf.2024.143249
Jin ZLi WBai YWang TLu YLiu WKim T(2024)Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper)Proceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473846(96-101)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473846

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents