research-article

On Endurance of Processing in (Nonvolatile) Memory

Authors:

Husrev Cilasun,

Zamshed Chowdhury,

Zhengyang Zhao,

Jian-Ping Wang,

Sachin Sapatnekar,

Ulya R. KarpuzcuAuthors Info & Claims

ISCA '23: Proceedings of the 50th Annual International Symposium on Computer Architecture

Article No.: 79, Pages 1 - 13

https://doi.org/10.1145/3579371.3589114

Published: 17 June 2023 Publication History

Abstract

Processing-in-Memory (PIM) architectures have gained popularity due to their ability to alleviate the memory wall by performing large numbers of operations within the memory itself. On top of this, nonvolatile memory (NVM) technologies offer highly energy-efficient operations, rendering processing in NVM especially promising. Unfortunately, a major drawback is that NVM has limited endurance. Even when used for standard memory, nonvolatile technologies face limited lifetimes, which is exacerbated by imbalanced usage of memory cells. PIM significantly increases the number of operations the memory is required to perform, making the problem much worse. In this work, we quantitatively analyze the impact of PIM applications on endurance considering representative memory technologies. Our findings indicate that limited endurance can easily block the performance and energy efficiency potential of PIM architectures. Even the best known technologies of today can fall short of meeting practical lifetime expectations. This highlights the importance of research efforts to improve endurance especially at the device technology level. Our study represents the first step in characterizing the very demanding endurance needs of PIM applications to derive a detailed technology level design specification.

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Cited By

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https://doi.org/10.3390/electronics14040712
Dahal SDhingra PThapa KPande PKalyanaraman A(2025)HpT: Hybrid Acceleration of Spatio-Temporal Attention Model Training on Heterogeneous Manycore ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.352278136:3(407-421)Online publication date: Mar-2025
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Padberg HRegev APiccolboni GBricalli AMolas GNodin JKvatinsky S(2024)Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism MemristorsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.330223571:1(395-399)Online publication date: Jan-2024
https://doi.org/10.1109/TCSII.2023.3302235
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cover image ACM Conferences

ISCA '23: Proceedings of the 50th Annual International Symposium on Computer Architecture

June 2023

1225 pages

ISBN:9798400700958

DOI:10.1145/3579371

Chair:
Yan Solihin,
General Chair:
Mark Heinrich
University of Central Florida

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 17 June 2023

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ISCA '23: 50th Annual International Symposium on Computer Architecture

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Cited By

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https://doi.org/10.3390/electronics14040712
Dahal SDhingra PThapa KPande PKalyanaraman A(2025)HpT: Hybrid Acceleration of Spatio-Temporal Attention Model Training on Heterogeneous Manycore ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.352278136:3(407-421)Online publication date: Mar-2025
https://doi.org/10.1109/TPDS.2024.3522781
Padberg HRegev APiccolboni GBricalli AMolas GNodin JKvatinsky S(2024)Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism MemristorsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.330223571:1(395-399)Online publication date: Jan-2024
https://doi.org/10.1109/TCSII.2023.3302235
Zhou HWu BCheng HLiu JLei TFeng DTong W(2024)DRCTL: A Disorder-Resistant Computation Translation Layer Enhancing the Lifetime and Performance of Memristive CIM Architecture2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00028(263-277)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00028
Pintus PDumont MShah VMurai TShoji YHuang DMoody GBowers JYoungblood N(2024)Integrated non-reciprocal magneto-optics with ultra-high endurance for photonic in-memory computingNature Photonics10.1038/s41566-024-01549-119:1(54-62)Online publication date: 23-Oct-2024
https://doi.org/10.1038/s41566-024-01549-1
Cui JLiu HCao Q(2024)Prospects and challenges of electrochemical random-access memory for deep-learning acceleratorsCurrent Opinion in Solid State and Materials Science10.1016/j.cossms.2024.10118732(101187)Online publication date: Sep-2024
https://doi.org/10.1016/j.cossms.2024.101187

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