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On driving many long wires in a VLSI layout

Published: 10 August 1986 Publication History

Abstract

It is assumed that long wires represent large capacitive loads, and the effect on the area of a VLSI layout when drivers are introduced along many long wires in the layout is investigated. A layout is presented for which the introduction of standard drivers along long wires squares the area of the layout; it is shown, however, that the increase in area is never greater than the layout's area squared if the driver can be laid out in a square region. This paper also shows an area-time trade-off for the driver of a single long wire of length / by which the area of the driver from Θ(l), to Θ(lq), q < l, can be reduced if a delay of Θ(ll-q) rather than Θ(log l) can be tolerated. Tight bounds are also obtained on the worst-case area increase in general layouts having these drivers.

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Cited By

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  • (1988)Testing and diagnosis of interconnects using boundary scan architectureInternational Test Conference 1988 Proceeding@m_New Frontiers in Testing10.1109/TEST.1988.207790(126-137)Online publication date: 1988
  • (1988)Optimal VLSI graph embeddings in variable aspect ratio rectanglesAlgorithmica10.1007/BF017621283:1-4(487-510)Online publication date: Nov-1988

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Andranik Mirzaian

To reduce the propagation delay along a long capacitive wire, a driver is inserted that creates a local expansion of the network. This expansion, in turn, increases the length of other wires. Since there are many long wires in the network, and each needs a driver, the effect on the network area of introducing drivers for these wires is studied. Tight lower and upper bounds are obtained. The method used is to formulate recurrence relations that model the effect of local expansions on all wire lengths. It is shown that, using standard drivers, the network area is at most squared, and this bound is tight. Among other results is an area-delay tradeoff result.

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Published In

cover image Journal of the ACM
Journal of the ACM  Volume 33, Issue 4
Oct. 1986
189 pages
ISSN:0004-5411
EISSN:1557-735X
DOI:10.1145/6490
Issue’s Table of Contents
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1986
Published in JACM Volume 33, Issue 4

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Cited By

View all
  • (1988)Testing and diagnosis of interconnects using boundary scan architectureInternational Test Conference 1988 Proceeding@m_New Frontiers in Testing10.1109/TEST.1988.207790(126-137)Online publication date: 1988
  • (1988)Optimal VLSI graph embeddings in variable aspect ratio rectanglesAlgorithmica10.1007/BF017621283:1-4(487-510)Online publication date: Nov-1988

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