Cited By
View all- Kalligeros EKavousianos XNikolos D(2006)Multiphase BISTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83361723:10(1429-1446)Online publication date: 1-Nov-2006
A highly regular multi-phase reseeding technique for scan-based BIST
Pages 295 - 298
Abstract
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. Also, a dynamic reseeding scheme is adopted for further reducing the required hardware overhead. A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage. Experimental results demonstrate the superiority of the proposed LFSR reseeding approach over the already known reseeding techniques.
References
[1]
M. Abramovici, M. A. Breuer & A. D. Friedman, Digital Systems Testing and Testable Design, Computer Sc. Press, NY, 1990.
[2]
P. H. Bardell, W. H. McAnney & J. Savir, Built-In Test for VLSI: PseudoRandom Techniques, John Wiley & Sons, 1987.
[3]
S. Hellebrand et al., "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Trans. Comp., Feb. 1995, pp. 223--233.
[4]
L. R. Huang et al., "Gauss-Elimination-Based Generation of Multiple Seed-Polynomial Pairs for LFSR", IEEE Trans. on CAD, vol. 16, no. 9, Sept. 1997, pp. 1015--1024.
[5]
E. Kalligeros et al., "A ROMless LFSR Reseeding Scheme for Scan-based BIST", Proc. of ATS, Nov. 2002, pp. 206--211.
[6]
E. Kalligeros et al., "An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST", Proc. 3rd IEEE ISQED, San Jose, CA, USA, March 2002, pp. 261--266.
[7]
G. Kiefer et al., "Application of Deterministic Logic BIST on Industrial Circuits", Proc. of ITC, Oct. 2000, pp. 105--114.
[8]
B. Koenemann, "LFSR-Coded Test Patterns for Scan Design", Proc. of ETC, April 1991, pp. 237--242.
[9]
C. V. Krishna et al., "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of ITC, Oct.-Nov. 2001, pp. 885--893.
[10]
H. K. Lee & D. S. Ha, "ATALANTA: An efficient ATPG for compbinational circuits", Dept. of Elect. Eng., Virginia Polytechnic Inst. and State Univ., Blacksburg, VA, USA, Tech. Rep. 93--12, 1993.
[11]
H.-G. Liang et al., "Two-Dimensional Test Data Compres-sion for Scan-Based Deterministic BIST", Proc. of ITC, Oct.-Nov. 2001, pp. 894--902.
[12]
J. Rajski et al., "Test Data Decompression for Multiple Scan Designs with Boundary Scan", IEEE Trans. on Computers, vol. 47, no. 11, Nov. 1998, pp. 1188--1200.
[13]
J. Rajski et al., "Embedded Deterministic Test for Low Cost Manufacuring Test", Proc. of ITC, Oct. 2002, pp. 301--310.
[14]
N. A. Touba & E. J. McCluskey, " Bit-Fixing in Pseudo-random Sequences for Scan BIST", IEEE Trans. on CAD, vol. 20, no. 4, April 2001, pp. 545--555.
[15]
H.-J. Wunderlich, "BIST for Systems-on-a-chip", Integration, the VLSI Journal, vol. 26, no. 1-2, December 1998, pp. 55--78.
[16]
N. Zacharia et al., "Decompression of Test Data Using Variable-Length Seed LFSRs", Proc. 13th VTS, Apr.-May 1995, pp. 426--433.
[17]
N. Zacharia et al., "Two Dimensional Test Data Decompressor for Multiple Scan Designs", Proc. of ITC, Oct. 1996, pp. 186--194.
[18]
"A Primitive Polynomial Search Program", http://users2.ev1. net/~sduplichan/primitivepolynomials/primitivepolynomials.htm.
Index Terms
- A highly regular multi-phase reseeding technique for scan-based BIST
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Published In
April 2003
320 pages
ISBN:1581136773
DOI:10.1145/764808
- General Chair:
- Mircea Stan,
- Program Chairs:
- David Garrett,
- Kazuo Nakajima
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Published: 28 April 2003
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View all- Kalligeros EKavousianos XNikolos D(2006)Multiphase BISTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83361723:10(1429-1446)Online publication date: 1-Nov-2006
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