Article

The best of both worlds: the efficient asynchronous implementation of synchronous specifications

Authors:

Abhijit Davare,

Kelvin Lwin,

Alex Kondratyev,

Alberto Sangiovanni-VincentelliAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 588 - 591

https://doi.org/10.1145/996566.996727

Published: 07 June 2004 Publication History

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Abstract

The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the description of two optimizations that decrease the overhead of desynchronization. First, we investigate the use of clustering to vary the granularity of desynchronization. Second, by applying temporal analysis on a formal execution model of the desynchronized design, we uncover significant amounts of timing slack. These methods are successfully applied to industrial RTL designs.

References

[1]

J. Cortadella, A. Kondratyev, L. Lavagno, C. Sotiriou, "A Concurrent Model for Desynchronization," IWLS 2003.

Google Scholar

[2]

J. P. Uyemura, "VLSI clocking and System Design" in Introduction to VLSI Circuits and Systems John Wiley & Sons, 2002.

Google Scholar

[3]

J. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits - Second Edition," Prentice Hall, 2003.

Digital Library

Google Scholar

[4]

A. Benveniste, L. Carloni, P. Caspi, A. Sangiovanni-Vincentelli. "Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment." Proceedings of EmSoft 2003.

Digital Library

Google Scholar

[5]

D. Chinnery and K. Keutzer, "Reducing the Timing Overhead," in Closing the Gap between ASIC and Custom: Tools and techniques for High-Performance ASIC design Kluwer Academic Publishers, 2002.

Google Scholar

[6]

Chu, Tam-Anh, "On the Models for Designing VLSI Asynchronous Digital Circuits," Integration, 4(2):99--113", June 1986.

Digital Library

Google Scholar

[7]

T. Murata, "Petri Nets: Properties, analysis and applications," Proceedings of the IEEE, pp. 541--580, Apr. 1989.

Crossref

Google Scholar

[8]

I. E. Sutherland. Micropipelines. Communications of the IEEE, Volume 32, Number 6, 1989.

Digital Library

Google Scholar

[9]

H. Hulgaard, S. M. Burns, T. Amon, and G. Borriello, "An algorithm for exact bounds on the time separation of events in concurrent systems," IEEE Transactions on Computers, 44(11):1306--1317, November 1995.

Digital Library

Google Scholar

[10]

R.M. Cormack, A review of classification (with Discussion). J. Roy. Stat. Soc. A 134:321--367, 1971.

Crossref

Google Scholar

Cited By

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Srivastava NManohar R(2018)Operation-Dependent Frequency Scaling Using DesynchronizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2885335(1-11)Online publication date: 2018
https://doi.org/10.1109/TVLSI.2018.2885335
Sadeghi RJahanirad H(2017)Performance-based clustering for asynchronous digital circuits2017 Iranian Conference on Electrical Engineering (ICEE)10.1109/IranianCEE.2017.7985445(238-243)Online publication date: May-2017
https://doi.org/10.1109/IranianCEE.2017.7985445
Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
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Index Terms

The best of both worlds: the efficient asynchronous implementation of synchronous specifications
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Information

Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Srivastava NManohar R(2018)Operation-Dependent Frequency Scaling Using DesynchronizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2885335(1-11)Online publication date: 2018
https://doi.org/10.1109/TVLSI.2018.2885335
Sadeghi RJahanirad H(2017)Performance-based clustering for asynchronous digital circuits2017 Iranian Conference on Electrical Engineering (ICEE)10.1109/IranianCEE.2017.7985445(238-243)Online publication date: May-2017
https://doi.org/10.1109/IranianCEE.2017.7985445
Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
Law CGwee BChang J(2011)Modeling and synthesis of asynchronous pipelinesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203950119:4(682-695)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2039501
Kounalakis ESotiriou C(2011)CPlaceProceedings of the 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2011.13(22-29)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.1109/ASYNC.2011.13
Beerel POzdag RFerretti M(2010)IntroductionA Designer's Guide to Asynchronous VLSI10.1017/CBO9780511674730.001(1-15)Online publication date: 26-Feb-2010
https://doi.org/10.1017/CBO9780511674730.001
Jin GWang LWang ZDai K(2007)An optimal design method for de-synchronous circuit based on control graphProceedings of the 7th international conference on Advanced parallel processing technologies10.5555/1785246.1785259(70-79)Online publication date: 22-Nov-2007
https://dl.acm.org/doi/10.5555/1785246.1785259
Jin GWang LWang ZDai K(2007)An Optimal Design Method for De-synchronous Circuit Based on Control GraphAdvanced Parallel Processing Technologies10.1007/978-3-540-76837-1_11(70-79)Online publication date: 2007
https://doi.org/10.1007/978-3-540-76837-1_11

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Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

A Framework for Modeling the Distributed Deployment of Synchronous Designs

Enabling adaptability through elastic clocks