Article

Application driven traffic modeling for NoCs

Authors:

Leonel Tedesco,

Leonardo Giacomet,

Fernando MoraesAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 62 - 67

https://doi.org/10.1145/1150343.1150364

Published: 28 August 2006 Publication History

Abstract

The network on chip (NoC) design process requires an adequate characterization of the application running on it to optimize communication resources utilization and dimensioning. The traffic modeling process is the most essential step for characterizing complex applications. It is possible to identify three methods to model traffic in NoC literature. The first one assumes sources continually send data at a constant rate to the network and it is the most commonly used. The second method employs probabilistic functions to model the traffic behavior for typical applications, as audio and video streams. The accuracy of this method is better, at the extra cost of modeling complexity and simulation time. The third method employs traffic traces to evaluate network performance. Even with small traces, simulation time can be prohibitive. The advantage is accuracy, superior to the previous models. Even if a given application is correctly modeled, other flows interfere on how the application traffic behaves within the network. Results about the mutual interference of different traffic flows in NoCs are scarce. This work has two main objectives: (i) compare NoC performance, in terms of throughput and latency, when different traffic models are used for the same application; (ii) evaluate the impact of network noise traffic on some specific modeled flow. Preliminary results show how far is the real NoC performance for a given application when an oversimplified model is employed. The conclusion is that NoCs must employ internal mechanisms to ensure QoS, since noise traffic makes modeled traffic to depart from its predicted behavior.

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Cited By

Liang HSang QHu CGong YCheng DZhou XWang Y(2023)TAPU: A Transmission-Analytics Processing Unit for Accelerating Multifunctions in IoT GatewaysIEEE Internet of Things Journal10.1109/JIOT.2023.327989210:20(18181-18197)Online publication date: 15-Oct-2023
https://doi.org/10.1109/JIOT.2023.3279892
Chaurasia A(2019)Performance of Synthetic Rosenblatt Process under Multicore Architecture2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA.2019.8822013(377-381)Online publication date: Jun-2019
https://doi.org/10.1109/ICECA.2019.8822013
Yin JKayiran OPoremba MJerger NLoh G(2016)Efficient synthetic traffic models for large, complex SoCs2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446073(297-308)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446073
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Index Terms

Application driven traffic modeling for NoCs
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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cover image ACM Conferences

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 August 2006

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SBCCI06

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SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Liang HSang QHu CGong YCheng DZhou XWang Y(2023)TAPU: A Transmission-Analytics Processing Unit for Accelerating Multifunctions in IoT GatewaysIEEE Internet of Things Journal10.1109/JIOT.2023.327989210:20(18181-18197)Online publication date: 15-Oct-2023
https://doi.org/10.1109/JIOT.2023.3279892
Chaurasia A(2019)Performance of Synthetic Rosenblatt Process under Multicore Architecture2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA.2019.8822013(377-381)Online publication date: Jun-2019
https://doi.org/10.1109/ICECA.2019.8822013
Yin JKayiran OPoremba MJerger NLoh G(2016)Efficient synthetic traffic models for large, complex SoCs2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446073(297-308)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446073
Moltchanov DAntonov AKluchev ABorunova KKustarev PPetrov VKoucheryavy YPlatunov A(2016)Statistical Traffic Properties and Model Inference for Shared Cache Interface in Multi-Core CPUsIEEE Access10.1109/ACCESS.2016.26031694(4829-4839)Online publication date: 2016
https://doi.org/10.1109/ACCESS.2016.2603169
Ma NZou ZLu ZZheng L(2015)Implementing MVC Decoding on Homogeneous NoCsProceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2015.48(387-391)Online publication date: 4-Mar-2015
https://dl.acm.org/doi/10.1109/PDP.2015.48
Ni WLiu Z(2015)A routing algorithm for Network-on-Chip with self-similar traffic2015 IEEE 11th International Conference on ASIC (ASICON)10.1109/ASICON.2015.7517177(1-4)Online publication date: Nov-2015
https://doi.org/10.1109/ASICON.2015.7517177
Ni JHao CWang NAi QYoshimura T(2015)Primal-dual method based simultaneous functional unit and register binding2015 IEEE 11th International Conference on ASIC (ASICON)10.1109/ASICON.2015.7516909(1-4)Online publication date: Nov-2015
https://doi.org/10.1109/ASICON.2015.7516909
Badr MJerger NYew PZhai AKeckler S(2014)SynFullProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665691(109-120)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.5555/2665671.2665691
Badr MJerger N(2014)SynFullACM SIGARCH Computer Architecture News10.1145/2678373.266569142:3(109-120)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.1145/2678373.2665691
Badr MJerger N(2014)SynFull: Synthetic traffic models capturing cache coherent behaviour2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)10.1109/ISCA.2014.6853236(109-120)Online publication date: Jun-2014
https://doi.org/10.1109/ISCA.2014.6853236
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