Institute for Computer Science

We present a new algorithm for k-layer straightline crossing minimization which is based on sifting that is a heuristic for dynamic reordering of decision diagrams used during logic synthesis and formal verification of logic circuits. The experiments prove sifting to be very efficient. In particular it outperforms the traditional layer by layer sweep based heuristics known from literature by far when applied to k-layered graphs with k ≥ 3.

The two most important frontend components of the VLSI design system CADIC are presented. The first one allows graphical specification of recursively defined circuits. The other one allows the designer to navigate across the synthesized layout following the hierarchical specification to check e.g. CADIC's hierarchical optimizations or to control the outcome of test (generation) algorithms.

We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn, and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the “conditional sum type” with delay ⩽tn (if it exists) together with a small complete test set with respect to the chosen fault model FM

We present an algebraic approach to hierarchical design of integrated circuits. This approach is based on a "calculus of nets" which includes topological as well as behavioural aspects of integrated circuits. We have developed a hierarchical design system called CADIC which is build around this calculus in much the same way as e.g. Algol is build around numerics. An example for the design of a family of fast adders will demonstrate the power of this calculus. Finally we will give a summary outline on the structure of procedures which automatically transform the design into lower design levels.

In this paper we study the effect of using information about (partial) symmetries for the minimization of reduced ordered binary decision diagrams (ROBDD's). The influence of symmetries for the integration in dynamic variable ordering is studied for both completely and incompletely specified Boolean functions.

This paper addresses the problem of establishing the unknown correspondence for the latch variables of two sequential circuits which have the same state encoding. This has direct application in flnite state machine veriflcation: If a one-to-one correspondence can be established between the latches of two circuits, then checking for their equivalence reduces t o a much simpler combinational equivalence check problem. The approach presented in this paper is based on methods used to solve the unknown correspondence problem for inputs and outputs in combinational circuits. It computes input and novel latch output signatures, using ROBDDs, for each latch variable of a circuit that help t o establish correspondence. Experimental results on a large set of benchmarks show the efficacy of this approach.

This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations. The permutation problem has several applications in the synthesis and verification of combinational logic: It arises in the technology mapping stage of logic synthesis and in logic verification. A popular method to solve it is to compute a signature for each variable that helps to establish a correspondence between the variables. Several researchers have suggested a wide range of signatures that have been used for this purpose. However, for each choice of signature, there remain variables that cannot be uniquely identified. Our research has shown that, for a given example, this set of problematic variables tends to be the same -regardless of the choice of signatures. The paper investigates this problem.

In this paper we deal with sensitivity analysis of combinatorial optimization problems and its fundamental term, the tolerance. For three classes of objective functions ( $\Sigma, \Pi, {\mbox{MAX}}$ ) we give some basic properties on upper and lower tolerances. We show that the upper tolerance of an element is well defined, how to compute the upper tolerance of an element, and give equivalent formulations when the upper tolerance is +∞ or > 0. Analogous results are given for the lower tolerance and some results on the relationship between lower and upper tolerances are given.

In this paper we deal with sensitivity analysis of combinatorial optimization problems and its fundamental term, the tolerance. For three classes of objective functions (Σ, Π, MAX) we give some basic properties on upper and lower tolerances. We show that the upper tolerance of an element is well defined, how to compute the upper tolerance of an element, and give equivalent formulations when the upper tolerance is +∞ or > 0. Analogous results are given for the lower tolerance and some results on the relationship between lower and upper tolerances are given.

Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression . However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we present an efficient architecture for computing DWT of images, which is based on a partitioned approach for lossy image compression . The architecture achieves its computational power by using pipelining and taking advantage of the flexible memory configurations available in FPGA's.

In this paper we present an efficient FPGA implementation of the 'Set Partitioning in Hierarchical Trees' (SPIHT) algorithm of Said and Pearlman [1] in combination with an arithmetic coder. The FPGA implementation is applied within a partitioned approach for wavelet-based lossy image compression [2]. The basic SPIHT algorithm uses dynamic data structures that make a hardware realization difficult. We illustrate in detail how these dynamic data structures can be implemented in the FPGA without the use of external memory. We present a hardware realization which can be run with a frequency of 40 MHz in a Xilinx XC4000 device. The design requires 23% less internal memory as the recently published algorithm 'SPIHT Image Compression without Lists' of Wheeler and Pearlman [5].

Discrete wavelet transformations (DWT) followed by embedded zerotree encoding (EZT) is a very efficient technique for image compression. However, the algorithms proposed in the literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding

Until recently verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time when applied to the class of Wallace-tree like multipliers

The contact minimization problem is the problem of determining which layers should be used for wiring the signal nets of a circuit, such that the total number of layer changes (called contacts or via holes) is minimized. In this paper we show how to use a polynomialtime algorithm to find a maximum matching for a graph to solve the contact minimization problem for two layers. Furthermore we show that the contact minimization problem for n layers is NP-complete for all fixed n≥3.

One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f1; . . . ; fm) : f0; 1g n ! f0;1g m have to deal with is nding sublogic which can be shared by di erent outputs, i.e., nding boolean functions = ( 1; . . . ; h) : f0;1g p ! f0; 1g h which can be used as common sublogic of good realizations of f1; . . . ; fm. In this paper we present an e cient robdd based implementation of this Common Decomposition Functions Problem (cdf). The key concept of our method is the exploitation of equivalences of the functions f1; . . . ; fm which considerably reduces the running time of the tool. Formally, cdf is de ned as follows: Given m boolean functions f1; . . . ; fm : f0;1g n ! f0;1g, and two natural numbers p and h, nd h boolean functions 1; . . . ; h : f0;1g p ! f0;1g such that 81 k m there is a decomposition of fk of the form fk(x1; . . . ; xn) = g (k) ( 1(x1; . . . ; xp); . . . ; h(x1; . . . ; xp); (k) h+1 (x1; . . . ; xp); . . . ; (k) r k (x1; . . . ; xp); xp+1; . . . ; xn) using a minimal number rk of single-output boolean decomposition functions.

Due to progress in VLSI technology, algorithm-oriented array architectures such as systolic arrays or bit-slice structures appear to be effective, feasible, and economic. The constrained-via-minimization problem for circuits composed of arrays of identical cells C is discussed. To guarantee identical electrical behavior of all instances of C and to allow further hierarchical processing, it is desirable to handle all instances of C identically. To this end, layer assignments of circuits needing a minimal number of via holes are sought. It is shown that this problem can be solved by embedding C on the torus, i.e. by identifying the northern boundary of C with the southern boundary, and the eastern one with the western one. The time complexity of the proposed algorithm is O(m3C), where mC is the number of routing segments in C

This paper investigates reduced ordered binary decision diagrams (OBDD) of partially symmetric Boolean functions when using variable orders where symmetric variables are adjacent. We prove upper bounds for the size of such symmetry ordered OBDDs (SymOBDD). They generalize the upper bounds for the size of OBDDs of totally symmetric Boolean functions and nonsymmetric Boolean functions proven by M.A. Heap and M.R. Mercer (1994) and I. Wegener (1984). Experimental results based on these upper bounds show that the nontrivial symmetry sets of a Boolean function should be located either right up at the beginning or right up at the end of the variable order in order to obtain best upper bounds