Institute for Computer Science

We present a new algorithm for k-layer straightline crossing minimization which is based on sifting that is a heuristic for dynamic reordering of decision diagrams used during logic synthesis and formal verification of logic circuits. The experiments prove sifting to be very efficient. In particular it outperforms the traditional layer by layer sweep based heuristics known from literature by far when applied to k-layered graphs with k ≥ 3.

We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn, and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the “conditional sum type” with delay ⩽tn (if it exists) together with a small complete test set with respect to the chosen fault model FM

In this paper we deal with sensitivity analysis of combinatorial optimization problems and its fundamental term, the tolerance. For three classes of objective functions ( $\Sigma, \Pi, {\mbox{MAX}}$ ) we give some basic properties on upper and lower tolerances. We show that the upper tolerance of an element is well defined, how to compute the upper tolerance of an element, and give equivalent formulations when the upper tolerance is +∞ or > 0. Analogous results are given for the lower tolerance and some results on the relationship between lower and upper tolerances are given.

Discrete wavelet transformations (DWT) followed by embedded zerotree encoding (EZT) is a very efficient technique for image compression. However, the algorithms proposed in the literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding

Until recently verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time when applied to the class of Wallace-tree like multipliers

The contact minimization problem is the problem of determining which layers should be used for wiring the signal nets of a circuit, such that the total number of layer changes (called contacts or via holes) is minimized. In this paper we show how to use a polynomialtime algorithm to find a maximum matching for a graph to solve the contact minimization problem for two layers. Furthermore we show that the contact minimization problem for n layers is NP-complete for all fixed n≥3.

Due to progress in VLSI technology, algorithm-oriented array architectures such as systolic arrays or bit-slice structures appear to be effective, feasible, and economic. The constrained-via-minimization problem for circuits composed of arrays of identical cells C is discussed. To guarantee identical electrical behavior of all instances of C and to allow further hierarchical processing, it is desirable to handle all instances of C identically. To this end, layer assignments of circuits needing a minimal number of via holes are sought. It is shown that this problem can be solved by embedding C on the torus, i.e. by identifying the northern boundary of C with the southern boundary, and the eastern one with the western one. The time complexity of the proposed algorithm is O(m3C), where mC is the number of routing segments in C

This paper investigates reduced ordered binary decision diagrams (OBDD) of partially symmetric Boolean functions when using variable orders where symmetric variables are adjacent. We prove upper bounds for the size of such symmetry ordered OBDDs (SymOBDD). They generalize the upper bounds for the size of OBDDs of totally symmetric Boolean functions and nonsymmetric Boolean functions proven by M.A. Heap and M.R. Mercer (1994) and I. Wegener (1984). Experimental results based on these upper bounds show that the nontrivial symmetry sets of a Boolean function should be located either right up at the beginning or right up at the end of the variable order in order to obtain best upper bounds