- Philippe J. Roussel is senior reliability research engineer at imec, supporting the DRE group on Statistics, SPC and ... morePhilippe J. Roussel is senior reliability research engineer at imec, supporting the DRE group on Statistics, SPC and Data Analysis since its start in 1984. He wrote a ML fitting program for analysis of statistical distri¬butions and acceleration models from reliability test data. From 1991 till 2000, he also worked on physico-chemical analysis techniques like µ-probe, TEM and SE for the MCA group. He co-authored papers in fields as diverse as handheld calculator programming, virology, SE, ESD, TDDB, EM, and TAD.edit
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TiN/a-Si/TiOx/TiN RRAM devices show non-linear I-V characteristics with analog and self-compliant switching. The non-filamentary switching is significant only above a current threshold, as determined using a soft breakdown detection... more
TiN/a-Si/TiOx/TiN RRAM devices show non-linear I-V characteristics with analog and self-compliant switching. The non-filamentary switching is significant only above a current threshold, as determined using a soft breakdown detection technique. Pulse monitoring and a-Si thickness variation experiments confirm that the current through the device is the dominant driving force for defect profile modulation in the TiOx switching layer. The current-accelerated defect movements results in self-compliant switching, eliminating the need for external current compliance for these devices.
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The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including... more
The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.
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... advanced CMOS technologies Guido Groeseneken', Robin Degraeve, Ben Kaczer and Philippe Roussel IMEC Kapeldreef 75, B-3001 Leuven, Belgium 'also at Katholieke Universiteit Leuven, Electricaf Engineering... more
... advanced CMOS technologies Guido Groeseneken', Robin Degraeve, Ben Kaczer and Philippe Roussel IMEC Kapeldreef 75, B-3001 Leuven, Belgium 'also at Katholieke Universiteit Leuven, Electricaf Engineering Department, Leuven, Belgium ...
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The authors study the statistical properties of individual defects in n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) using time dependent defect spectroscopy. This technique is based on the analysis of quantized... more
The authors study the statistical properties of individual defects in n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) using time dependent defect spectroscopy. This technique is based on the analysis of quantized threshold voltage transients observed on nanoscaled p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) after negative stress and provides the characteristic emission and capture times of individual traps. To complement to previous studies, the authors apply the methodology to SiON nMOSFETs and positive bias temperature stress. The authors demonstrate that the relaxation transients are due to the collective behavior of individual traps. Furthermore, a strong temperature dependence is observed for both emission and capture times. This is incompatible with elastic tunneling theory which is used in trap characterization techniques such as charge pumping, and also in simulations of erase and program transients of nonvolatile memories. The c...
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We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier... more
We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions th...
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STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent... more
STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent studies show that a significant error is made using the conventional methods for Δ extraction. We investigate the origin of the low accuracy. To reduce the error down to 5%, 1000 cycles or multiple ramp rates are necessary. Furthermore, the thermal stabilities extracted from current switching and magnetic field switching appear to be uncorrelated and this cannot be explained by a macrospin model. Measurements at different temperatures show that self-heating together with a domain wall model can explain these uncorrelated Δ. Characterizing self-heating properties is therefore crucial to correctly determine the thermal stability.
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In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is... more
In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is stochastic, voltage and temperature dependent, and widely distributed in time, resulting in each device behaving very differently during operation (Fig. 1) [1,2].
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ABSTRACT The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (V-G similar to... more
ABSTRACT The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (V-G similar to V-D/2). At higher V-G closer to V-D, cold and hot carrier injection to the oxide bulk defect increases and dominates at the V-G = V-D stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to V-G and highly at V-G = V-D, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.
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With the rise of neuromorphic computing, oxide resistive RAM (OxRRAM) has received a lot of attention as potential electronic synapse. A frequently used function in neuromorphic applications is the computationally powerful winner-take-all... more
With the rise of neuromorphic computing, oxide resistive RAM (OxRRAM) has received a lot of attention as potential electronic synapse. A frequently used function in neuromorphic applications is the computationally powerful winner-take-all (WTA) operation. Implementing synapses with OxRRAM devices and implementing the WTA operation with a dedicated circuit introduces an inaccuracy in obtaining the winning neuron due to OxRRAM variability and comparator offset. While winner-take-all neural networks are often used, a comprehensive variability analysis of those networks is still missing. In this work, a complete device-circuit-algorithm analytic analysis framework is developed to assess the WTA accuracy in neural networks. This framework is demonstrated on a multi-layer perceptron in OxRRAM followed by the WTA circuit. It is quantified how the classification accuracy degrades with increasing device and circuit variability. The framework sets out the boundary conditions for reliably using WTA circuits for typical OxRRAM devices. The analytic expressions in this paper are generally valid for all types of RRAM.
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Amorphous Vacancy Modulated Conductive Oxide resistive switching devices achieve non-localized low current switching by electrical modulation of defect distribution. We present for the first time a quantitative model to explain the... more
Amorphous Vacancy Modulated Conductive Oxide resistive switching devices achieve non-localized low current switching by electrical modulation of defect distribution. We present for the first time a quantitative model to explain the operation of these devices. The defect movements are accelerated by lowering of potential barrier under electric field. Using this model, we successfully explain the observed switching characteristics of gradual and analog switching, reset during set bias due to over-programming, along with some insight on the fresh state. We also elucidate its endurance and retention characteristics and discuss a methodology to estimate the number of defects responsible for switching.
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We can think of thin oxide layer degradation by electrical stress as the continuous generation of point defects in the layer. The exact trap generation mechanism is still under discussion. Basically, two ideas have been proposed in... more
We can think of thin oxide layer degradation by electrical stress as the continuous generation of point defects in the layer. The exact trap generation mechanism is still under discussion. Basically, two ideas have been proposed in literature: one assumes direct involvement of the electric field (electrochemical model) [1], the second proposes a current-driven mechanism with the defectgenerating species being either holes [2] or hydrogen [3]. Several recently performed dedicated experiments favor the current driven model [4] but the nature of the degrading species is still not certain. In this paper, it is not our intention to describe in detail the microscopic structure of the oxide defects, neither to discuss their exact generation mechanism. It suff ices to state that 1) the traps are mostly neutral, 2) they can trap electrons and 3) they are generated at random places in the bulk of the layer. A statistical treatment of the random generation pattern with the introduction of elec...
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Amorphous Vacancy Modulated Conductive Oxide resistive switching devices (TiN/a-Si/TiOx/TiN) are attractive for storage class memory applications due to their self-rectifying and self-compliant characteristics with low current switching.... more
Amorphous Vacancy Modulated Conductive Oxide resistive switching devices (TiN/a-Si/TiOx/TiN) are attractive for storage class memory applications due to their self-rectifying and self-compliant characteristics with low current switching. However, the endurance is intrinsically limited to 103 cycles. Using specific experiments and insights from kinetic defect distribution models, we identify two modes of failure - first, window closure to the middle due to defect loss and profile symmetrization as the consequences of current and field driven-defect profile modulation, respectively, and second, excess defect generation at higher bias culminating in dielectric breakdown. Based on these findings, we suggest improvement to the device stack.
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In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is... more
In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3µm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100?C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications. Display Omitted Reliability of two 3×50µm TSV compatible metallization schemes is investigated.TDDB data are impacted by interactions between Si scallops and liner conformality.The scalable one shows more sensitivity to local field enhancement at high field.Their performance at operation fields meets standard reliability specifications.
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... Title: Stress polarity dependence of degradation and breakdown of SiO2/high-k stacks. Authors:Degraeve, Robin × Kauerauf, Thomas Kerber, Andreas Cartier, E Govoreanu, Bogdan Roussel, Philippe Pantisano, Luigi Blomme, Pieter Kaczer,... more
... Title: Stress polarity dependence of degradation and breakdown of SiO2/high-k stacks. Authors:Degraeve, Robin × Kauerauf, Thomas Kerber, Andreas Cartier, E Govoreanu, Bogdan Roussel, Philippe Pantisano, Luigi Blomme, Pieter Kaczer, Ben Groeseneken, Guido. ...
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ABSTRACT In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over... more
ABSTRACT In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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ABSTRACT In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO2/Al2O3 n-MOSFET. Trap density has been scanned either in energy or in position based on... more
ABSTRACT In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO2/Al2O3 n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO2 interface.
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ABSTRACT Measuring and understanding TDDB reliability in sub- 1nm EOT dielectrics is both a practical and scientific challenge. We present three different methods for the experimental determination of the SBD and wearout parameters needed... more
ABSTRACT Measuring and understanding TDDB reliability in sub- 1nm EOT dielectrics is both a practical and scientific challenge. We present three different methods for the experimental determination of the SBD and wearout parameters needed to construct an all-in-one TDDB reliability prediction consisting of a SBD-free region, a leakage current-dominated region and a HBD-limited region. We demonstrate these methods on several sub-1nm EOT high-k/metal gate nMOS and pMOS devices and evaluate their advantage and disadvantages. We also discuss the validity and interpretation of the SBD/wearout model, confronting it with experiments that demonstrate how SBD paths can be annealed by reversing the stress polarity.
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... Acknowledgements The financial support of Siemens AG for this work is greatly acknowledged. Also, the authors are very grateful to Paul Hendrickx, Guido Vanhorebeek, Marc Van Dievel, Frank Vleugels and Geert Van den bosch. References... more
... Acknowledgements The financial support of Siemens AG for this work is greatly acknowledged. Also, the authors are very grateful to Paul Hendrickx, Guido Vanhorebeek, Marc Van Dievel, Frank Vleugels and Geert Van den bosch. References ...
Research Interests: Engineering, Computer Science, IEEE, Capacitor, Iedm, and 4 moreElectron Devices, PROM, EU-SILC, and Flash Photography
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KULeuven. ...
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This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single... more
This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single layers to SiO2(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO2 (or
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We propose a compact model description of the entire I<inf>d</inf>-V<inf>g</inf> characteristic, based on the EKV model, and extended to capture the complex I<inf>d</inf>-V<inf>g</inf>... more
We propose a compact model description of the entire I<inf>d</inf>-V<inf>g</inf> characteristic, based on the EKV model, and extended to capture the complex I<inf>d</inf>-V<inf>g</inf> distortion induced by asymmetric hot carrier degradation. In particular, we apply the methodology to model the degradation of pMOS devices during off-state hot carrier stress, which is a reliability concern relevant for memory periphery applications.