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TiN/a-Si/TiOx/TiN RRAM devices show non-linear I-V characteristics with analog and self-compliant switching. The non-filamentary switching is significant only above a current threshold, as determined using a soft breakdown detection... more
TiN/a-Si/TiOx/TiN RRAM devices show non-linear I-V characteristics with analog and self-compliant switching. The non-filamentary switching is significant only above a current threshold, as determined using a soft breakdown detection technique. Pulse monitoring and a-Si thickness variation experiments confirm that the current through the device is the dominant driving force for defect profile modulation in the TiOx switching layer. The current-accelerated defect movements results in self-compliant switching, eliminating the need for external current compliance for these devices.
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The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including... more
The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.
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... advanced CMOS technologies Guido Groeseneken', Robin Degraeve, Ben Kaczer and Philippe Roussel IMEC Kapeldreef 75, B-3001 Leuven, Belgium 'also at Katholieke Universiteit Leuven, Electricaf Engineering... more
... advanced CMOS technologies Guido Groeseneken', Robin Degraeve, Ben Kaczer and Philippe Roussel IMEC Kapeldreef 75, B-3001 Leuven, Belgium 'also at Katholieke Universiteit Leuven, Electricaf Engineering Department, Leuven, Belgium ...
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The authors study the statistical properties of individual defects in n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) using time dependent defect spectroscopy. This technique is based on the analysis of quantized... more
The authors study the statistical properties of individual defects in n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) using time dependent defect spectroscopy. This technique is based on the analysis of quantized threshold voltage transients observed on nanoscaled p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) after negative stress and provides the characteristic emission and capture times of individual traps. To complement to previous studies, the authors apply the methodology to SiON nMOSFETs and positive bias temperature stress. The authors demonstrate that the relaxation transients are due to the collective behavior of individual traps. Furthermore, a strong temperature dependence is observed for both emission and capture times. This is incompatible with elastic tunneling theory which is used in trap characterization techniques such as charge pumping, and also in simulations of erase and program transients of nonvolatile memories. The c...
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We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier... more
We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions th...
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STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent... more
STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent studies show that a significant error is made using the conventional methods for Δ extraction. We investigate the origin of the low accuracy. To reduce the error down to 5%, 1000 cycles or multiple ramp rates are necessary. Furthermore, the thermal stabilities extracted from current switching and magnetic field switching appear to be uncorrelated and this cannot be explained by a macrospin model. Measurements at different temperatures show that self-heating together with a domain wall model can explain these uncorrelated Δ. Characterizing self-heating properties is therefore crucial to correctly determine the thermal stability.
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In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is... more
In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is stochastic, voltage and temperature dependent, and widely distributed in time, resulting in each device behaving very differently during operation (Fig. 1) [1,2].
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ABSTRACT The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (V-G similar to... more
ABSTRACT The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (V-G similar to V-D/2). At higher V-G closer to V-D, cold and hot carrier injection to the oxide bulk defect increases and dominates at the V-G = V-D stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to V-G and highly at V-G = V-D, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.
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With the rise of neuromorphic computing, oxide resistive RAM (OxRRAM) has received a lot of attention as potential electronic synapse. A frequently used function in neuromorphic applications is the computationally powerful winner-take-all... more
With the rise of neuromorphic computing, oxide resistive RAM (OxRRAM) has received a lot of attention as potential electronic synapse. A frequently used function in neuromorphic applications is the computationally powerful winner-take-all (WTA) operation. Implementing synapses with OxRRAM devices and implementing the WTA operation with a dedicated circuit introduces an inaccuracy in obtaining the winning neuron due to OxRRAM variability and comparator offset. While winner-take-all neural networks are often used, a comprehensive variability analysis of those networks is still missing. In this work, a complete device-circuit-algorithm analytic analysis framework is developed to assess the WTA accuracy in neural networks. This framework is demonstrated on a multi-layer perceptron in OxRRAM followed by the WTA circuit. It is quantified how the classification accuracy degrades with increasing device and circuit variability. The framework sets out the boundary conditions for reliably using WTA circuits for typical OxRRAM devices. The analytic expressions in this paper are generally valid for all types of RRAM.
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Amorphous Vacancy Modulated Conductive Oxide resistive switching devices achieve non-localized low current switching by electrical modulation of defect distribution. We present for the first time a quantitative model to explain the... more
Amorphous Vacancy Modulated Conductive Oxide resistive switching devices achieve non-localized low current switching by electrical modulation of defect distribution. We present for the first time a quantitative model to explain the operation of these devices. The defect movements are accelerated by lowering of potential barrier under electric field. Using this model, we successfully explain the observed switching characteristics of gradual and analog switching, reset during set bias due to over-programming, along with some insight on the fresh state. We also elucidate its endurance and retention characteristics and discuss a methodology to estimate the number of defects responsible for switching.
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We can think of thin oxide layer degradation by electrical stress as the continuous generation of point defects in the layer. The exact trap generation mechanism is still under discussion. Basically, two ideas have been proposed in... more
We can think of thin oxide layer degradation by electrical stress as the continuous generation of point defects in the layer. The exact trap generation mechanism is still under discussion. Basically, two ideas have been proposed in literature: one assumes direct involvement of the electric field (electrochemical model) [1], the second proposes a current-driven mechanism with the defectgenerating species being either holes [2] or hydrogen [3]. Several recently performed dedicated experiments favor the current driven model [4] but the nature of the degrading species is still not certain. In this paper, it is not our intention to describe in detail the microscopic structure of the oxide defects, neither to discuss their exact generation mechanism. It suff ices to state that 1) the traps are mostly neutral, 2) they can trap electrons and 3) they are generated at random places in the bulk of the layer. A statistical treatment of the random generation pattern with the introduction of elec...
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Amorphous Vacancy Modulated Conductive Oxide resistive switching devices (TiN/a-Si/TiOx/TiN) are attractive for storage class memory applications due to their self-rectifying and self-compliant characteristics with low current switching.... more
Amorphous Vacancy Modulated Conductive Oxide resistive switching devices (TiN/a-Si/TiOx/TiN) are attractive for storage class memory applications due to their self-rectifying and self-compliant characteristics with low current switching. However, the endurance is intrinsically limited to 103 cycles. Using specific experiments and insights from kinetic defect distribution models, we identify two modes of failure - first, window closure to the middle due to defect loss and profile symmetrization as the consequences of current and field driven-defect profile modulation, respectively, and second, excess defect generation at higher bias culminating in dielectric breakdown. Based on these findings, we suggest improvement to the device stack.
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In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is... more
In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3µm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100?C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications. Display Omitted Reliability of two 3×50µm TSV compatible metallization schemes is investigated.TDDB data are impacted by interactions between Si scallops and liner conformality.The scalable one shows more sensitivity to local field enhancement at high field.Their performance at operation fields meets standard reliability specifications.
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... Title: Stress polarity dependence of degradation and breakdown of SiO2/high-k stacks. Authors:Degraeve, Robin × Kauerauf, Thomas Kerber, Andreas Cartier, E Govoreanu, Bogdan Roussel, Philippe Pantisano, Luigi Blomme, Pieter Kaczer,... more
... Title: Stress polarity dependence of degradation and breakdown of SiO2/high-k stacks. Authors:Degraeve, Robin × Kauerauf, Thomas Kerber, Andreas Cartier, E Govoreanu, Bogdan Roussel, Philippe Pantisano, Luigi Blomme, Pieter Kaczer, Ben Groeseneken, Guido. ...
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ABSTRACT In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over... more
ABSTRACT In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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ABSTRACT In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO2/Al2O3 n-MOSFET. Trap density has been scanned either in energy or in position based on... more
ABSTRACT In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO2/Al2O3 n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO2 interface.
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ABSTRACT Measuring and understanding TDDB reliability in sub- 1nm EOT dielectrics is both a practical and scientific challenge. We present three different methods for the experimental determination of the SBD and wearout parameters needed... more
ABSTRACT Measuring and understanding TDDB reliability in sub- 1nm EOT dielectrics is both a practical and scientific challenge. We present three different methods for the experimental determination of the SBD and wearout parameters needed to construct an all-in-one TDDB reliability prediction consisting of a SBD-free region, a leakage current-dominated region and a HBD-limited region. We demonstrate these methods on several sub-1nm EOT high-k/metal gate nMOS and pMOS devices and evaluate their advantage and disadvantages. We also discuss the validity and interpretation of the SBD/wearout model, confronting it with experiments that demonstrate how SBD paths can be annealed by reversing the stress polarity.
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... Acknowledgements The financial support of Siemens AG for this work is greatly acknowledged. Also, the authors are very grateful to Paul Hendrickx, Guido Vanhorebeek, Marc Van Dievel, Frank Vleugels and Geert Van den bosch. References... more
... Acknowledgements The financial support of Siemens AG for this work is greatly acknowledged. Also, the authors are very grateful to Paul Hendrickx, Guido Vanhorebeek, Marc Van Dievel, Frank Vleugels and Geert Van den bosch. References ...
Research Interests: Engineering, Computer Science, IEEE, Capacitor, Iedm, and 4 moreElectron Devices, PROM, EU-SILC, and Flash Photography
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KULeuven. ...
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This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single... more
This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single layers to SiO2(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO2 (or
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We propose a compact model description of the entire I<inf>d</inf>-V<inf>g</inf> characteristic, based on the EKV model, and extended to capture the complex I<inf>d</inf>-V<inf>g</inf>... more
We propose a compact model description of the entire I<inf>d</inf>-V<inf>g</inf> characteristic, based on the EKV model, and extended to capture the complex I<inf>d</inf>-V<inf>g</inf> distortion induced by asymmetric hot carrier degradation. In particular, we apply the methodology to model the degradation of pMOS devices during off-state hot carrier stress, which is a reliability concern relevant for memory periphery applications.
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In high aspect ratio TSV's, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be... more
In high aspect ratio TSV's, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3 micron and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctri) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.
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A unified compact modeling framework of device aging is proposed and verified on FinFET technology. For this purpose, the simplified EKV (sEKV) model is used for modeling the transfer characteristics and converting the stress current into... more
A unified compact modeling framework of device aging is proposed and verified on FinFET technology. For this purpose, the simplified EKV (sEKV) model is used for modeling the transfer characteristics and converting the stress current into carrier velocity-electric field profile. By combining this profile with TCAD simulations of the electric field along the channel, a simplified device representation consisting of a series of channel slices is constructed, which facilitates 2D degradation modeling performed in each slice by integrating oxide charge trapping, interface degradation due to Si-H bond breaking, and impact ionization. Our approach allows accurate reliability-enabled compact modeling across the entire bias space. Good agreement between experimental and simulated transfer characteristics is achieved. The calibrated model further reveals the complex interplays between different degradation mechanisms, consistent with previous reports.
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A unified compact modeling framework of device aging is proposed and verified on FinFET technology. For this purpose, the simplified EKV (sEKV) model is used for modeling the transfer characteristics and converting the stress current into... more
A unified compact modeling framework of device aging is proposed and verified on FinFET technology. For this purpose, the simplified EKV (sEKV) model is used for modeling the transfer characteristics and converting the stress current into carrier velocity-electric field profile. By combining this profile with TCAD simulations of the electric field along the channel, a simplified device representation consisting of a series of channel slices is constructed, which facilitates 2D degradation modeling performed in each slice by integrating oxide charge trapping, interface degradation due to Si-H bond breaking, and impact ionization. Our approach allows accurate reliability-enabled compact modeling across the entire bias space. Good agreement between experimental and simulated transfer characteristics is achieved. The calibrated model further reveals the complex interplays between different degradation mechanisms, consistent with previous reports.
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Abstract-The statistical distribution of negative bias temperature instability (NBTI) in deca-nanometer p-channel FETs is discussed. An exponential distribution of threshold voltage shifts due to a single charge trapped in the gate oxide... more
Abstract-The statistical distribution of negative bias temperature instability (NBTI) in deca-nanometer p-channel FETs is discussed. An exponential distribution of threshold voltage shifts due to a single charge trapped in the gate oxide is observed, resulting in single-charge shifts exceeding 30 mV in some of the studied 35-nm-long and 90-nm-wide devices. The exponential distribution is justified with a simple channel percolation model. Combined with the assumption of the Poisson-distributed number of trapped gate oxide charges, an analytical description of the total NBTI threshold voltage shift distribution is derived. This allows, among other things, linking its first two moments with the average number of defects per device, which is found < 10 in the studied devices. Index Terms-MOSFETs, negative bias temperature instability (NBTI), reliability, variability.
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With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of... more
With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of technology and keep predicting accurately and efficiently the high-level design metrics such as delay and power. Although it is the most time consuming, Monte Carlo is still the simplest and
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Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process... more
Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.
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The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching, the triggering of snapback and the CDM-specific bipolar saturation... more
The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. The optimal gate length for ...
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ABSTRACT We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either with Si passivation and conventional SiO2/HfO2 gate stack, or with GeOx/high-k gate stacks. A general model for understanding this phenomenon in... more
ABSTRACT We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either with Si passivation and conventional SiO2/HfO2 gate stack, or with GeOx/high-k gate stacks. A general model for understanding this phenomenon in alternative substrate/dielectric systems is proposed. We discuss two different approaches to pursue a reduction of charge trapping in alternative material systems, which will be necessary for achieving reliable high-mobility devices.
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ABSTRACT The variability of 1T FBRAM performances is investigated. The VG read window and the state &quot;1&quot; distribution are correlated with the number of holes injected during the write &quot;1&quot; related to the... more
ABSTRACT The variability of 1T FBRAM performances is investigated. The VG read window and the state &quot;1&quot; distribution are correlated with the number of holes injected during the write &quot;1&quot; related to the electric field in the S/D junctions. Besides, the origin of wide retention time distribution has been correlated with the distribution of G-R center in the Si band gap. Single defect with the Si midgap energy level can generate a leakage path affecting strongly the cell retention time. This can explain also wide retention distribution. Thight control of such defects poses extreme challange for the manufacturing of FBRAM.
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers... more
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers to each other is a simple yet effective method to significantly increase the compound stack yield. In this paper, we present a mathematical model, which shows that the yield increase depends on (1) the number of stack tiers, (2) the number of dies per wafer, (3) the die yield, and (4) the repository size. Simulation results demonstrate that, for realistic cases, relative yield increases of 0.5% to 10% can be achieved. We also show that the required investment, in terms of a limited increase in either test or package costs, is typically well justified.
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ABSTRACT In this paper we review a dynamic device model for filamentary RRAM in HfO-based dielectrics. We summarize its transient modeling features and its statistical properties. The model explains with satisfactory quantitative... more
ABSTRACT In this paper we review a dynamic device model for filamentary RRAM in HfO-based dielectrics. We summarize its transient modeling features and its statistical properties. The model explains with satisfactory quantitative resolution all main features of the RRAM switching, not just the voltage, time and temperature dependence, but also statistical fluctuations resulting from atomistic motion and their resulting LRS and HRS-distributions.
ABSTRACT Although scaled down technologies may suffer from statistical parameter fluctuations caused by process variability, they are potentially radiation hard from a total-dose perspective. Therefore, the proton radiation hardness of a... more
ABSTRACT Although scaled down technologies may suffer from statistical parameter fluctuations caused by process variability, they are potentially radiation hard from a total-dose perspective. Therefore, the proton radiation hardness of a high-kappa/metal gate 45 nm CMOS technology is studied using wafer level testing on 300 mm wafers. Attention is given to the correlation between pre-and post-radiation parameter variations. It is demonstrated that both the preirradiation process variability and the radiation-induced variability of the parameters have to be taken into account. For devices with a capping layer, the type of dielectric layer has an impact on the radiation-induced trapping mechanisms.
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Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers... more
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers to
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ABSTRACT Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V (_{rm TH}) shifts... more
ABSTRACT Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V (_{rm TH}) shifts and fluctuations, which are even visible during the I (_{D}) –V (_{G}) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times (tau _{c}) and (tau _{e}) , and their impact on V (_{rm TH}) as a function of gate voltage V (_{G}) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V (_{G}) swing and operational temperatures.
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ABSTRACT Process variation affects the soft-error sensitivity of SRAM cells. A complex dependence on the arrival time of the particle strike relative to the word-line clock is observed.
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ABSTRACT We calculate band offsets for FinFETs with strained SiGeand strained InGaAs-channels on strain relaxed buffers (SRB) and provide specific guidelines to optimize quantum wells, metal gate work functions, and mobilities for... more
ABSTRACT We calculate band offsets for FinFETs with strained SiGeand strained InGaAs-channels on strain relaxed buffers (SRB) and provide specific guidelines to optimize quantum wells, metal gate work functions, and mobilities for group-IV and group-III/V devices. Quantum well carrier confinement of 200 meV (or greater) for the channel strongly improves DIBL and SS for 10 nm-node FinFETs. Such quantum wells can be achieved for the following combinations: a strained-Si channel nFinFET on a Si0.6Ge0.4 SRB; a strained Si0.4Ge0.6 channel pFinFET on a Si substrate; or an In0.53Ga0.47As channel nFinFET on In0.52Al0.48As/InP. When increasing the In% above 70% for InGaAs channel nFETs, sufficient band offset is also achieved when the channel is directly grown on an InP or an In0.4Ga0.6As SRB. Both nand pFinFETs with SiGe-channels require n-type work function metals, while p-type work functions are needed for InGaAs-channel nFinFETs. Therefore a dual-work function gate scheme is required to co-integrate InGaAs nFETs and SiGe pFETs.
ABSTRACT For future high density storage memories, 3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative because of the extreme reduction of cost per bit (1-3). This architecture, however, faces critical... more
ABSTRACT For future high density storage memories, 3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative because of the extreme reduction of cost per bit (1-3). This architecture, however, faces critical reliability issues related to the highly defective channel (4-5). For instance, we recently showed that discrete current drops and fluctuations (RTN) are clearly observed in the transfer characteristics (ID vs. VG) of these nanoscale vertical nFETs (Fig. 1). These instabilities were linked to single electron trapping/detrapping processes (6-7), which potentially may cause read errors during operation (4-5). The present paper therefore aims at characterizing these adverse switching traps to gain insight into their physical properties. A statistical comparison among different polysilicon channels is presented and benchmarked against monocrystalline planar nFETs. We reveal that a significant part of the switching traps reside in the poly-Si channel.
Particle removal without damage addition remains a grand challenge. Particle removal and damage addition are macroscopic effects of the cleaning technique. In order to improve the understanding of cleaning techniques like... more
Particle removal without damage addition remains a grand challenge. Particle removal and damage addition are macroscopic effects of the cleaning technique. In order to improve the understanding of cleaning techniques like high-velocity-aerosol cleaning, these ...
... Thomas Kauerauf, Geni Butera, Kristof Croes, Steven Demuynck, Christopher J. Wilson, Philippe Roussel, Chris Drijbooms, Hugo Bender, Melina Lofrano, Bart Vandevelde, Zsolt Tőkei, Guido Groeseneken ... [14] I. Vos, D. Hellin, S.... more
... Thomas Kauerauf, Geni Butera, Kristof Croes, Steven Demuynck, Christopher J. Wilson, Philippe Roussel, Chris Drijbooms, Hugo Bender, Melina Lofrano, Bart Vandevelde, Zsolt Tőkei, Guido Groeseneken ... [14] I. Vos, D. Hellin, S. Demuynck, O. Richard, T. Conard, J. Vertommen ...
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Wafer thinning, one of the key enabling techniques for 3D integration, is widely studied due to its impact on Si breakage strength. However, most studies only focused on the average strength, without checking the failure mechanisms. This... more
Wafer thinning, one of the key enabling techniques for 3D integration, is widely studied due to its impact on Si breakage strength. However, most studies only focused on the average strength, without checking the failure mechanisms. This may result in misleading conclusions and the mechanism of breakage is still ambiguous. In this paper, the mechanical strength of wafers that were thinned using different methods [rough grinding(RG), fine grinding(FE), plasma etching(PE), chemical mechanical polishing(CMP)] was evaluated statistically and through failure analysis. The results provide the industry guidance on their wafer thinning strategy. Si wafers were thinned down to 300μm by different thinning techniques: only RG; RG+FG; RG+FG+10μm CMP and RG+FG+10μm PE. Next the samples were diced into strips and the strength was tested using a 4-point bending test. The breakage strength of the dies was plotted in Weibull graphs and on wafer maps. Both RG and PE samples showed a strong bimodal di...
Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent... more
Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent Dielectric Breakdown (TDDB) lifetime, which was also predicted by simulations. Comparison of TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35nm HP Cu interconnects confirms
As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the state-of-the-art, dynamic energy consumption and power... more
As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the state-of-the-art, dynamic energy consumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose
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Abstract For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by... more
Abstract For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, ...
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ABSTRACT Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving... more
ABSTRACT Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving circuit lifetime. This paper proposes a comprehensible compact model for reliability simulation of analog integrated circuits. The proposed model includes all typical NBTI peculiarities such as relaxation after voltage stress reduction and dependence on time-varying stress voltage and temperature. Comprising both the recoverable and permanent NBTI components, the model also offers a significant accuracy improvement over existing models such as the popular Reaction-Diffusion model. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Further, the model includes only 10 process-dependent parameters, enabling easy calibration. The model is validated on a 1.9nm EOT SiON CMOS process.
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ABSTRACT The correlation of discrete gate and drain current fluctuations is revealed in nanoscaled SiON pFETs and nFETs, demonstrating that discrete trapping and detrapping events in the same single states are responsible of both ID and... more
ABSTRACT The correlation of discrete gate and drain current fluctuations is revealed in nanoscaled SiON pFETs and nFETs, demonstrating that discrete trapping and detrapping events in the same single states are responsible of both ID and IG random telegraph noise (RTN). The high and low gate current IG-RTN levels are independent of temperature but the switching rates thermally activated indicating that the trapping and detrapping events are consistent with nonradiative multiphonon theory.
This paper presents an approach for statistical characterization of standard cells based on a combination of Statistical Design of Experiments (S-DoE) and Response Surface Modeling. Unlike both, most of the State-of-the-Art and... more
This paper presents an approach for statistical characterization of standard cells based on a combination of Statistical Design of Experiments (S-DoE) and Response Surface Modeling. Unlike both, most of the State-of-the-Art and Sensitivity Analysis (SA) techniques currently oered by EDA vendors, S-DoE preserves the underlying correlation among process variation parameters. This results in about two orders of magnitude of statistical accuracy improvement, yet it features an electrical simulation eort linear to the cell complexity. The technique is validated using a representative subset of standard cells using a 32nm statistical Physical Design Kit.
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ABSTRACT Recently germanium MOSFETs have attracted attention due to the promising carrier mobility of germanium compared to silicon. To understand the germanium MOSFET interface, the conductance interface trap density extraction technique... more
ABSTRACT Recently germanium MOSFETs have attracted attention due to the promising carrier mobility of germanium compared to silicon. To understand the germanium MOSFET interface, the conductance interface trap density extraction technique was verified for the first time on germanium MOSFETs. In order to know the characteristics of the (near-) interface traps it is essential to confirm the validity of the model on which their extraction is based. It cannot be simply assumed that the interface will behave as in Si. For this purpose low temperature measurements were performed at 80 K and a variation on the ac conductance technique was developed. Typical Si impedance behavior is found for Ge but Si extraction methods cannot be applied to Ge capacitors in general. Indications for weak Fermi-level pinning near the conduction band were found in Si-passivated Ge/HfO2 capacitors. This explains the weak performance of the corresponding nMOSFET.
ABSTRACT In this paper we review some advances in High-κ characterization by means of capacitance measurement in the radio-frequency regime (widely known as RFCV). Firstly, we present a robust methodology for the gate impedance parameter... more
ABSTRACT In this paper we review some advances in High-κ characterization by means of capacitance measurement in the radio-frequency regime (widely known as RFCV). Firstly, we present a robust methodology for the gate impedance parameter extraction in short channel leaky devices, based on measurements from DC to the GHz range and fitting with a robust weighted algorithm. Secondly, we will present a novel RFCV technique which pushes the conventional split-CV measurement to the MHz range. This RF-split-CV is based on measuring with a 2-port network analyzer, as opposed to the conventional technique which uses a 1 port LCR meter. This improved technique is the basis for accurate mobility extraction as studied in the final part of the paper. This methodology takes parasitics fully into account: the RF-split-CV curves obtained are used for the accurate metallurgical channel length extraction. Combination of these Lmet results with conventional Ids Vgs curves measured in the linear regime leads to the source and drain resistance calculation. After all these corrections have been performed, the mobility is finally calculated.
ABSTRACT In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold... more
ABSTRACT In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.
ABSTRACT We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on... more
ABSTRACT We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.
Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The... more
Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The analysis is done by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique [1] varying charge injection time and gate voltage independently. Varying time determines the physical charge
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This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate... more
This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to `see&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;#39; the device transient response is presented in this paper with experimental
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ABSTRACT With the continuous downscaling of CMOS device dimensions, (i) The number of gate oxide defects in each device decreases to a numerable level, while their relative impact on the device characteristics increases. (ii) The... more
ABSTRACT With the continuous downscaling of CMOS device dimensions, (i) The number of gate oxide defects in each device decreases to a numerable level, while their relative impact on the device characteristics increases. (ii) The properties of each defect, such as its capture and emission times and its impact, are voltage and/or temperature dependent and widely distributed. (iii) The occupation kinetics of each defect is known to be stochastic. All of these result in each of the nominally identical nm-scaled devices behaving very differently during operation, resulting in increasing time-dependent variability (heteroskedasticity). Consequently, the lifetime of nm-sized devices cannot be predicted individually, but can be described in terms of time- (or workload-) dependent distributions.
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ABSTRACT With a significantly reduced Negative Bias Temperature Instability (NBTI), SiGe channel pMOSFETs promise to virtually eliminate this reliability issue for ultra-thin EOT devices. The intrinsically superior NBTI robustness of the... more
ABSTRACT With a significantly reduced Negative Bias Temperature Instability (NBTI), SiGe channel pMOSFETs promise to virtually eliminate this reliability issue for ultra-thin EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. Other reliability mechanisms such as low-frequency noise, channel hot carriers, and time-dependent dielectric breakdown are shown not to be showstoppers.
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ABSTRACT Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold VTH voltage of advance CMOS technologies. Furthermore, a reduction of the positive VTH drift (instability) has been... more
ABSTRACT Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold VTH voltage of advance CMOS technologies. Furthermore, a reduction of the positive VTH drift (instability) has been reported for rare-earth doped nFETs under positive gate bias stress at high temperature. However, a non-optimized process can lead to an anomalous VTH behavior. We demonstrate that two independent components are responsible for this anomalous behavior which can be decoupled, individually studied, and then projected for meaningful lifetime extrapolations.
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... Dig. - Int. Electron Devices Meet. 2002, 509. SSTana, TPChen, JMSoon, KPLoh, CHAng, and L.Chan, Nitrogen-enhanced negative bias temperature instability: An insight by experiment and first-principle calculations, Appl. Phys. Lett.... more
... Dig. - Int. Electron Devices Meet. 2002, 509. SSTana, TPChen, JMSoon, KPLoh, CHAng, and L.Chan, Nitrogen-enhanced negative bias temperature instability: An insight by experiment and first-principle calculations, Appl. Phys. Lett. 82, 1881 (2003). ...
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ABSTRACT We study the variability of microdose effects induced by heavy-ion strikes on FinFETs. We model the effects through a statistical analysis, which considers the three-dimensional nature of these devices and overlapping ion hits.... more
ABSTRACT We study the variability of microdose effects induced by heavy-ion strikes on FinFETs. We model the effects through a statistical analysis, which considers the three-dimensional nature of these devices and overlapping ion hits. The analysis carried out in this work is based on a large amount of experimental data and on the reliability distribution functions (Poisson area scaling, LogNormal distribution, Weibull distribution, etc.), commonly used to estimate the time and charge to breakdown for accelerated lifetime tests.
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ABSTRACT This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions... more
ABSTRACT This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures.
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ABSTRACT New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested... more
ABSTRACT New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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AbstractA detailed study on charge trapping and dielectric re-liability of SiO2Al2O3 gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were... more
AbstractA detailed study on charge trapping and dielectric re-liability of SiO2Al2O3 gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The ...
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Oxide breakdown is one of the most threatening failure mechanisms in integrated circuits. As the oxide thickness is decreased in the sub-5nm range, the breakdown definition itself is no longer clear and its . detection becomes... more
Oxide breakdown is one of the most threatening failure mechanisms in integrated circuits. As the oxide thickness is decreased in the sub-5nm range, the breakdown definition itself is no longer clear and its . detection becomes problematic. A new algorithm for accurate and . ...
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ABSTRACT A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and... more
ABSTRACT A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.
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A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different... more
A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example.
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The measurement of the entire $I_{D}$– $V_{G}$ characteristic of a nanoscaled pMOSFET before and after the capture of a single elementary charge in a gate-oxide defect is demonstrated. The impact of a single trapped carrier on the device... more
The measurement of the entire $I_{D}$– $V_{G}$ characteristic of a nanoscaled pMOSFET before and after the capture of a single elementary charge in a gate-oxide defect is demonstrated. The impact of a single trapped carrier on the device characteristics is compared with 3-D atomistic device simulations. The $I_{D}$–$V_{G}$ behavior is identified to depend on the location of the oxide defect
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This work assesses the impact of process variability such as device mismatch of two in-house FinFET and a planar technology on key figures of merit (SNM and WTP) of SRAMs – for the first time not only at cell but also at product level. We... more
This work assesses the impact of process variability such as device mismatch of two in-house FinFET and a planar technology on key figures of merit (SNM and WTP) of SRAMs – for the first time not only at cell but also at product level. We show that the statistical cell response in the very end of the tails is the key metric that determines SRAM yield, which is quite different between the SRAM cell and its array. Statistical VCCmin analysis shows that for small arrays, supply voltage in planar is limited to around 1V, in doped Bulk-FF (BFF) to 0.9V, while undoped SOIFF reaches 0.6V. Meanwhile, VCC limits for array sizes are 512Kbit at 1V for planar, 2Mbit at 0.9V FOR BFF, and – far ahead – at least 1GBit at 0.7V for undoped SOIFF devices. Supported by an AVt sensitivity analysis, it appears to be the introduction of full depletion that forms the prime choice criteria of that device for SRAM implementations.
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ABSTRACT A calibration methodology for transient analysis of voltage and current waveforms during VFTLP testing is presented. An OPEN, SHORT and LOAD calibration are required to de-embed the probe needles and system parasitics. This... more
ABSTRACT A calibration methodology for transient analysis of voltage and current waveforms during VFTLP testing is presented. An OPEN, SHORT and LOAD calibration are required to de-embed the probe needles and system parasitics. This enables the use of non-RF probes for VFTLP measurements, resulting in a lower cost and higher measurement flexibility for VFTLP testing.
In order to maintain the trend of ever-increasing performance, several directions have been pursued by the semiconductor industry in the past decade. i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k... more
In order to maintain the trend of ever-increasing performance, several directions have been pursued by the semiconductor industry in the past decade. i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates, ii) new (3D) device architectures are being developed, iii) devices are downscaled toward atomic dimensions, while iv) supply voltages are not correspondingly reduced.