The goal of the design and optimization phase in analog integrated circuits conception is to get the structure yielding the best system performance. The parameters of various components (resistance, capacitance, transistors, etc) of the... more
The goal of the design and optimization phase in analog integrated circuits conception is to get the structure yielding the best system performance. The parameters of various components (resistance, capacitance, transistors, etc) of the circuit are set to the optimized nominal values, but no guarantee exists that these values will be conserved during the fabrication process. As a matter of
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of... more
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.
The implementation of a VHDL-AMS to SPICE converter (Vhdl2Spice) to be inserted in a complete CAD environment [1] is described. Vhdl2Spice generates a SPICE netlist by tracing down the VHDL IIR parse tree available from the already... more
The implementation of a VHDL-AMS to SPICE converter (Vhdl2Spice) to be inserted in a complete CAD environment [1] is described. Vhdl2Spice generates a SPICE netlist by tracing down the VHDL IIR parse tree available from the already existing VHDL analyzer. ...
A low-voltage fully differential CMOS operational amplifier withconstant-gmand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel... more
A low-voltage fully differential CMOS operational amplifier withconstant-gmand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output
A configuration for the realization of voltage-mode second-order filters employing a single operational transresistance amplifier (OTRA) as the active element is presented. This topology can synthesize lowpass, highpass, bandpass, notch... more
A configuration for the realization of voltage-mode second-order filters employing a single operational transresistance amplifier (OTRA) as the active element is presented. This topology can synthesize lowpass, highpass, bandpass, notch and allpass filtering functions. The presented filters are suitable for MOS-C implementation, yielding the filter parameters to be electronically tunable. Theoretical analysis is verified with PSPICE simulation.
In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New... more
In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here
Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the... more
Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.
This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental... more
This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental results for 2 µm CMOS technology are provided.
We solve the manufacturing problem of identifying the model statistical parameters ensuring a satisfactory quality of analog circuits produced in a photolithographic process. We formalize it in a statistical framework as the problem of... more
We solve the manufacturing problem of identifying the model statistical parameters ensuring a satisfactory quality of analog circuits produced in a photolithographic process. We formalize it in a statistical framework as the problem of inverting the mapping from the population of the circuit production variables to the performances’ population. Both variables and performances are random. From a sample of the joint population we want to identify the statistical features of the former producing a performance distribution that satisfies the design constraints with a good preassigned probability. The key idea of the solution method we propose consists of describing the above mapping in terms of a mixture of granular functions, where each is responsible for a fuzzy set within the input-output space, hence for a cluster therein. The way of synthesizing the whole space as a mixture of these clusters is learnt directly from the examples. As a result we have an analytical form both of the mapping approximating complex Spice models in terms of polynomials in the production variables, and of the distribution law of the induced performances that allows a relatively quick and easy management of the production variables’ statistical parameters as a function of the probability with which we plan to satisfy the design constraint. We apply the method to case studies and real production data where our method outperforms current methods’ running times and accuracies.
This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim... more
This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x−y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-μm, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.
In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The... more
In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration ...