VLSI signal processing

In this paper, we present the IRIS architectural synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. By incorporating a novel synthesis methodology, called the Modular Design Procedure, within the IRIS system, parameterised models of complex and innovative DSP hardware can be derived and automatically assembled to create new DSP systems. ...

In this paper we present a pipeline architecture specifically designed for processing of DNA microarray images. Many of the pixilated image generation methods produce one row of the image at a time. This property is fully exploited by a pipeline which takes in one row of the produced image at each clock pulse and performs the necessary image processing steps on it. This will remove the present need for sluggish software routines that are considered a major bottleneck in the microarray technology. The size of the proposed structure is a function of the width of the image and not its length. The proposed architecture is proved to be highly modular, scalable and suited for a Standard Cell VLSI implementation.

The implementation of a VHDL-AMS to SPICE converter (Vhdl2Spice) to be inserted in a complete CAD environment [1] is described. Vhdl2Spice generates a SPICE netlist by tracing down the VHDL IIR parse tree available from the already existing VHDL analyzer. ...

The primary focus of the paper is on the development of an intelligent control scheme, which is insensitive to parametric uncertainty, load and parameter fluctuations and most importantly amenable for real time implementation. In this paper, we present a stable Lateral Fuzzy Controller (LAFC) for an outdoor Autonomously Guided Vehicle (AGV), which is a converted electrically powered golf-car. The controller

In this paper, we present preliminary results comparing the nature of the errors introduced by the mixture of principal components (MPC) model with a wavelet transform and the Karhunen Loève transform (KLT) for the lossy compression of brain magnetic resonance (MR) images. MPC, wavelets and KLT were applied to image blocks in a block transform coding scheme. The MPC model partitions the space of image blocks into a set of disjoint classes and computes a separate KLT for each class. In our experiments, though both the wavelet transform and KLT obtained a higher peak signal to noise ratio (PSNR) than MPC, according to radiologists, MPC preserved the texture and boundaries of gray and white matter better than the wavelet transform or KLT.

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.

An audio fingerprint is a compact content-based signature that summarizes an audio recording. Audio Fingerprinting technologies have attracted attention since they allow the identification of audio independently of its format and without the need of meta-data or watermark embedding. Other uses of fingerprinting include: integrity verification, watermark support and content-based audio retrieval. The different approaches to fingerprinting have been described with different rationales and terminology: Pattern matching, Multimedia (Music) Information Retrieval or Cryptography (Robust Hashing). In this paper, we review different techniques describing its functional blocks as parts of a common, unified framework.

We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.

This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules and operating at the transfer speed of 622 Mbits/sec. The processing modules and memory banks communicate through a low cost interconnection scheme able though to perform at system's required data transfer rate. The entire system constitutes a component which can accommodate a switching system as an intelligent buffer with real time processing and multiplexing capabilities. The component performs operations on fixed and/or variable length packets of data on a stream basis. The architecture embeds both the processing and the memory modules, thus producing a “system on a chip” solution.

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of this task. High level design tools are used to develop the test bench VHDL code. The test bench code models sensors which drive the Model Under Test (MUT). Data files which can also drive the MUT are prepared by environmental data generators. The system specification values are linked to the testbench via requirements capture tools and test plans. Intelligent interfaces are used to control the development and simulation of the test bench. The approach is applicable to the testing of any DSP system modeled in the VHDL language. It provides the modeler with the capability to rapidly test DSP models and adjust the model test environment to frequent changes in system requirements.

IEEE 802.22, also called Wireless Regional Area Network (WRAN), is the newest wireless standard being developed for remote and rural areas. In this paper an overview of the standard, and more specifically its PHY layer is introduced. In order to evaluate the performance of the system, we model the PHY layer in MATLAB/SIMULINK and extract the Bit Error Rate (BER) of the system for different code rates and modulation schemes with noisy channel.

In this paper, a novel architecture of a floating-point digital signal processor is presented. It introduces a single hardware structure with a full set of elementary arithmetic functions which includessin, cos, tan, arctanh, circular rotation andvectoring, sinh, cosh, tanh, arctanh, hyperbolic rotation andvectoring, square root, logarithm, exponential as well asaddition, multiplication anddivision. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) and the Convergence Computing Method (CCM) algorithms for computing arithmetic functions and it is fully parallel and pipelined. Its advanced functionality is achieved without significant increase in hardware, in comparison to ordinary CORDIC processor, and makes it an ideal processing element in high speed multiprocessor applications, e.g. real time Digital Signal Processing (DSP) and computer graphics.

... MPEG-4 Systems al-lows to describe any piece of audio-visual information in time as part of ... 1 shows how a scene with multiple objects is treated by MPEG-4. Video, audio and 3D ... In a finalrendering and compositing step, the scene is composed from the decoded objects using ...

We show that two antenna array pattern synthesis problems can be expressed as convex optimization problems. The first one deals with a symmetric planar array with real weights, which can be expressed as a linear program. The second one concerns a broadband acoustic array, which becomes a convex quadratically constrained quadratic program. Because these two problems are convex, they can be (numerically) solved with great efficiency by recently developed interior-point methods. Thanks to the efficiency of the interior point methods, we also built a computer-aided design tool for the first problem.

In this paper, an FPGA model of RC servo and Stepper motor control system was built. This system consists of EP2C5T144C8 Cyclone II Mini Board, 9 grams micro servo motor, 28BYJ-48 Stepper Motor, ULN2003 motor driver. This system operates 3 functions parallelly, a simple binary count with the 3 LEDs on the board, from 0 to 7, controlling a RC servo, where the position is dependent on the value in the previous counter. The servo starts when the counter value goes from 000 to 001 for the first time. After counting from 0 to 7 for the first time, the servo goes to its initial position when the counter goes to 000 for all the time and controlling a Stepper motor, where the speed is dependent again on the previous counter. The proposed model is built using Verilog HDL, simulated using Modelsim Altera Starter Edition 10.1d and synthesized using Xilinx ISE 9.2i package, and will be implemented using Cyclone II FPGA Mini Board kit. Implementation and Simulation behavioral model results show ...

International Conference on Signal Processing and Communication - ICSPC'17
July 28-29 2017 Coimbatore, Tamil Nadu, India

The conference aims to bring together the Scientists, Scholars, Engineers, Industrialists and Students from in and around the world to present and share their knowledge and experience on the on-going research activities and hence to foster research relations between universities and industries. This conference provides opportunities for the delegates to exchange new ideas, insights, applications and experiences, to establish research relations and to find global partners for collaborations and to solve future problems in signal processing and communication.

=== Important Dates ===

March 15, 2017........................Tutorial  Special Session proposals
March 15, 2017.........................Paper submission deadline
April 15, 2017........................... Notification of acceptance
April 30, 2017............................Camera-ready paper submission
July 28-29, 2017........................ICSPC17 Conference

The authors are invited to submit technical papers of their original, unpublished work under the below-mentioned sub-themes. The works within the broad areas (but not limited to) are acceptable for the presentation in the conference.

Track 1
Bio-Signal Processing
Audio/Speech Processing and Coding
Statistical Signal Processing
Signal Processing for Communications
Medical Image Processing
Array Signal Processing
Soft Computing for Image Processing
Remote Sensing
Signal Processing for Security
Video Processing
Biometrics
Cryptography/Steganography/Watermarking
VLSI Signal Processing

Track 2

Mobile and Cellular Communications
Vehicular Communication Networks
Wireless Sensor Networks
Antennas, RF, and Microwave Communications
Optical Communication
MIMO and Space-Time Communications
Cognitive Radio and Cognitive Networks
Satellite Communication
Virtual Reality and Gaming
OFDM and CDMA Communication Receivers