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ABSTRACT Selective attention is a very efficient strategy for engineering active vision systems that need to extract relevant information from the scene in real-time. We propose an implementation of a saliency-map based active vision... more
ABSTRACT Selective attention is a very efficient strategy for engineering active vision systems that need to extract relevant information from the scene in real-time. We propose an implementation of a saliency-map based active vision system in which Address-Event sensors and neuromorphic winner-take-all devices complement conventional imagers and machine vision components. A standard imager is mounted next to a Dynamic Vision Sensor (DVS) on a Pan-Tilt Unit. The output of the DVS is fed to an event-based Selective Attention Chip that implements a Winner-Take-All network with inhibition of return, to identify and sequentially select the most salient regions in the visual input space, and drive the Pan-Tilt Unit accordingly. We characterize the system with experiments using real-world scenarios and natural scenes, and interface it to a workstation to implement models of top-down attention used to influence the decision making process.
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ABSTRACT Progress in VLSI technologies is enabling the integration of large numbers of spiking neural network processing modules into compact systems. Asynchronous routing circuits are typically employed to efficiently interface these... more
ABSTRACT Progress in VLSI technologies is enabling the integration of large numbers of spiking neural network processing modules into compact systems. Asynchronous routing circuits are typically employed to efficiently interface these modules, and configurable memory is usually used to implement synaptic connectivity among them. However, supporting arbitrary network connectivity with conventional routing methods would require prohibitively large memory resources. We propose a two stage routing scheme which minimizes the memory requirements needed to implement scalable and reconfigurable spiking neural networks with bounded connectivity. Our routing methodology trades off network configuration flexibility for routing memory demands and is optimized for the most common and anatomically realistic neural network topologies. We describe and analyze our routing method and present a case study with a large neural network.
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The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting... more
The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framew...
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Cooperative competitive networks are believed to play a central role in cortical processing and have been shown to exhibit a wide set of useful computational properties. We propose a VLSI implementation of a spiking cooperative compet-... more
Cooperative competitive networks are believed to play a central role in cortical processing and have been shown to exhibit a wide set of useful computational properties. We propose a VLSI implementation of a spiking cooperative compet- itive network and show how it can perform context dependent computation both in the mean firing rate domain and in spike timing correlation space.
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This demonstration will show a distributed VLSI neuromorphic system implementing the soft Winner-Take-All (WTA) operation using spiking neurons. It also shows how recurrently connected instances of them can have persistent activity... more
This demonstration will show a distributed VLSI neuromorphic system implementing the soft Winner-Take-All (WTA) operation using spiking neurons. It also shows how recurrently connected instances of them can have persistent activity states, which can used for state-dependent computation. The live demonstration of this network will show that the position of a localized stimulus can be tracked and remembered along a