- Arta, Epirus, Greece
A desired property of an autonomous system is the capability to operate and survive in unforeseen conditions. Wireless IoT (formerly Wireless Sensor Network) applications, pose a series of limitations regarding an embedded system’s power... more
A desired property of an autonomous system is the capability to operate and survive in unforeseen conditions. Wireless IoT (formerly Wireless Sensor Network) applications, pose a series of limitations regarding an embedded system’s power consumption and energy autonomy. The PERPS project proposes an innovative approach to energy harvesting systems, aiming to perpetual operation of WSN nodes and portable electronics. A state-of-the-art energy conversion integrated circuit (ENC IC), with real-time S/W algorithms is implemented, to allow the predictive estimation of energy availability at the system’s installation site. A multi-source input is employed combining parallel harvesters for various energy sources including (ambient) light, (micro) vibrations and (small) temperature differences, to upgrade the topology’s efficiency and versatility. In addition, the newly-introduced concept of harvesting energy via triboelectric microgenerators is studied. Ultra-low power consumption microelectronic circuitries and novel storage structure techniques are employed in order the overall architecture to present optimum energy utilization, therefore maximized efficiency. The final version of the system will be tested on a ship’s engine room thus the verification of the PERPS project operational principle will be based on real and demanding environmental conditions.
Research Interests:
A desired property of an autonomous system is the capability to operate and survive in unforeseen conditions. Wireless IoT (formerly Wireless Sensor Network) applications, pose a series of limitations regarding an embedded system’s power... more
A desired property of an autonomous system is the capability to operate and survive in unforeseen conditions. Wireless IoT (formerly Wireless Sensor Network) applications, pose a series of limitations regarding an embedded system’s power consumption and energy autonomy. The PERPS project proposes an innovative approach to energy harvesting systems, aiming to perpetual operation of WSN nodes and portable electronics. A state-of-the-art energy conversion integrated circuit (ENC IC), with real-time S/W algorithms is implemented, to allow the predictive estimation of energy availability at the system’s installation site. A multi-source input is employed combining parallel harvesters for various energy sources including (ambient) light, (micro) vibrations and (small) temperature differences, to upgrade the topology’s efficiency and versatility. In addition, the newly-introduced concept of harvesting energy via triboelectric microgenerators is studied. Ultra-low power consumption microele...
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This work presents an ultra-low-power CMOS supercapacitor storage unit suitable for a plethora of low-power autonomous applications. The proposed unit exploits the unregulated voltage output of harvesting circuits (i.e., DC-DC converters)... more
This work presents an ultra-low-power CMOS supercapacitor storage unit suitable for a plethora of low-power autonomous applications. The proposed unit exploits the unregulated voltage output of harvesting circuits (i.e., DC-DC converters) and redirects the power to the storage elements and the working loads. Being able to adapt to the input energy conditions and the connected loads’ supply demands offers extended survival to the system with the self-startup operation and voltage regulation. A low-complexity control unit is implemented which is composed of power switches, comparators and logic gates and is able to supervise two supercapacitors, a small and a larger one, as well as a backup battery. Two separate power outputs are offered for external load connection which can be controlled by a separate unit (e.g., microcontroller). Furthermore, user-controlled parameters such as charging and discharging supercapacitor voltage thresholds, provide increased versatility to the system. T...
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Evolving applications related to video technologies require video encoder and decoder implemented with low cost and achieving real-time performance. In order to meet this demand and targeting especially the applications imposing low VLSI... more
Evolving applications related to video technologies require video encoder and decoder implemented with low cost and achieving real-time performance. In order to meet this demand and targeting especially the applications imposing low VLSI area requirements, the present paper describes a VLSI H.264/AVC encoder architecture performing at real-time. The encoder uses a pipeline architecture and all the modules have been optimized
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ABSTRACT In this P y we present an efficient Terminal Adapter for the Broadband ntegrated Services Digital Network (B-ISDN). The adapter performs in the Asynchronous Transfer Mode (ATM) environment. It is optimized for efficient transfer... more
ABSTRACT In this P y we present an efficient Terminal Adapter for the Broadband ntegrated Services Digital Network (B-ISDN). The adapter performs in the Asynchronous Transfer Mode (ATM) environment. It is optimized for efficient transfer of bulk data, while maintaining ...
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In this paper we examine the methodology, architectural issues and preliminary statistical results for identifying the presence and position of a given query clip within a massive collection of video content. This work is part of the... more
In this paper we examine the methodology, architectural issues and preliminary statistical results for identifying the presence and position of a given query clip within a massive collection of video content. This work is part of the European Union FP6 1ST Programme project DIVAS (Direct Video & Audio Content Search Engine). The concept is applicable to a number of use
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ABSTRACT It is a common understanding that the surveillance video market is moving to standard, wireline and wireless IP based solutions because of the many advantages over the proprietary RF-based solutions that were deployed previously.... more
ABSTRACT It is a common understanding that the surveillance video market is moving to standard, wireline and wireless IP based solutions because of the many advantages over the proprietary RF-based solutions that were deployed previously. State of the art solutions are using the very popular H.264 standard for the video compression. Surveillance video applications differentiate from other video streaming applications in the fact that the delivery of the video has to be very reliable, thus, especially for wireless environments, the usage of UDP as transmission mechanism is not the ideal solution. On the other hand, surveillance video potentially needs to be distributed to many viewers, something that would significantly increase the bandwidth usage if a non UDP-multicasting transmission is used. In this work a solution is proposed to the problem of transmission of surveillance video in a reliable manner, by combining the best of both worlds: An intermediate multicast video server is used for receiving video streams through TCP from the IP camera and transmitting through multicast UDP to the viewers. An implementation of our proposal is described and experimental results are presented and verify the proposed methodology.
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... D. Reisis, N. Vlassopoulos Electronics Laboratory, Department of Physics National and Kapodistrian University of Athens Athens, Greece dreisis@phys.uoa.gr G. Doumenis, G. Georgakarakos, J. Sifnaios Global Digital Technologies Athens,... more
... D. Reisis, N. Vlassopoulos Electronics Laboratory, Department of Physics National and Kapodistrian University of Athens Athens, Greece dreisis@phys.uoa.gr G. Doumenis, G. Georgakarakos, J. Sifnaios Global Digital Technologies Athens, Greece gregory.doumenis@ ...
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This paper presents a decomposition of the SSCOP [1] protocol, which is based on the detailed analysis of the performance of the layer. The protocol decomposition aims at mapping the various functions of the SSCOP layer onto modules with... more
This paper presents a decomposition of the SSCOP [1] protocol, which is based on the detailed analysis of the performance of the layer. The protocol decomposition aims at mapping the various functions of the SSCOP layer onto modules with optimized running speed when these are applied on modern network processors ([2], [3], [4]). The SSCOP layer is a mandatory part of the ATM Signalling Adaptation Layer (SAAL [5]). The running time performance of the SSCOP has a significant impact on the execution speed of the entire layer. A mapping of the SSCOP most complex functions onto dedicated hardware units leads to accommodating the requirement of speeding up the SSCOP execution. This work analyzes the protocol into primitive functions and presents the performance of the functions that are executed frequently during ATM call setup and tear-down. The measurements from the protocol's profiling lead to a partitioning of the functions, in order to implement a subset of these in hardware and ...
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The authors describe a terminal adapter which connects a personal computer to the broadband integrated services digital network based on the asynchronous transfer mode technique. They show that the low cost and modular architecture of the... more
The authors describe a terminal adapter which connects a personal computer to the broadband integrated services digital network based on the asynchronous transfer mode technique. They show that the low cost and modular architecture of the adapter provides a powerful platform serving broadband applications. They present four classes of communication applications which have been built or they are under development: bulk data transfer, interactive data transfer, interworking communication and multimedia applications. They describe the architecture of each application class and address performance issues in respect to the communication parameters
In this paper we evaluate the efficiency of a Terminal Adapter, hosted by a personal computer as well as measurements evaluating the implementation of the ATM protocol in hardware and software modules. We present various implementations... more
In this paper we evaluate the efficiency of a Terminal Adapter, hosted by a personal computer as well as measurements evaluating the implementation of the ATM protocol in hardware and software modules. We present various implementations with respect to system and transfer parameters which have a significant impact on the effective throughput. We show results deriving from the measurements to be used in setting up and optimizing a Terminal Adapter for ATM networks.
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Abstract A motion estimation architecture allowing the execution of a variety of block-matching search techniques is presented in this paper. The ability to choose the most efficient search technique with respect to speeding up the... more
Abstract A motion estimation architecture allowing the execution of a variety of block-matching search techniques is presented in this paper. The ability to choose the most efficient search technique with respect to speeding up the process and locating the best matching target block leads ...
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Network processors utilize a special unit for the classifi- cation of the received packets according to their character- istics. The classification of packets is currently the most processor intensive portion of network processing which... more
Network processors utilize a special unit for the classifi- cation of the received packets according to their character- istics. The classification of packets is currently the most processor intensive portion of network processing which has to be performed at wire speed. Currently, network processors use Content Addressable Memories (CAM), for classification of thousands of flow identifiers in ATM and IP, with very long keys. This paper proposes an alterna- tive method for searching wide keys, using RAM chips as storage medium instead of the expensive and complex CAMs. The technique relies on the open-addressing hash- ing methodology to provide high speed lookups close to the CAM's performance. It also handles efficiently the limitations imposed by the hashing algorithms by select- ing properly the parameters of the system.
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This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3)... more
This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules and operating at the transfer speed of 622 Mbits/sec. The processing modules and memory banks communicate through a low cost interconnection scheme able though to perform at system's required data transfer rate. The entire system constitutes a component which can accommodate a switching system as an intelligent buffer with real time processing and multiplexing capabilities. The component performs operations on fixed and/or variable length packets of data on a stream basis. The architecture embeds both the processing and the memory modules, thus producing a “system on a chip” solution.
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In this paper we present the experience gained from the design and verification of a complex network processor. The processor can operate in either ATM or IP based multiprotocol networking environments, supporting link rates up to 2.4... more
In this paper we present the experience gained from the design and verification of a complex network processor. The processor can operate in either ATM or IP based multiprotocol networking environments, supporting link rates up to 2.4 Gbps. We describe the methodology followed during the verification process, from specifications to silicon prototype test and highlight the problems encountered during the post-layout procedure. To accommodate the application verification a proprietary Debug Tool is integrated in the system. The paper emphasizes the importance of the verification, addressing it as a parallel process to system design, and highlights the need for easy to verify designs.
This paper presents an Intelligent Shared Buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture,... more
This paper presents an Intelligent Shared Buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks.
This paper presents a simple and reusable Test Access Mechanism for SaGs. The introduced architecture is based on the re-use of existing interconnect structures, such as on-chip buses, for testing purposes. The proposed scheme acts... more
This paper presents a simple and reusable Test Access Mechanism for SaGs. The introduced architecture is based on the re-use of existing interconnect structures, such as on-chip buses, for testing purposes. The proposed scheme acts twofold: for testing, as a medium to transfer test stimuli to the system modules, and for system monitoring and application functional verification, tracing the transactions upon the system internal bus. Our system is particularly suitable for SaGs implementing packet based communication applications.
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ABSTRACT This paper presents a VLSI architecture specifically designed to support emerging video/data communication/multiplexing applications as a video/communication controller in an ATM network. Using a shared memory with efficient... more
ABSTRACT This paper presents a VLSI architecture specifically designed to support emerging video/data communication/multiplexing applications as a video/communication controller in an ATM network. Using a shared memory with efficient interconnection the design can accommodate either a processing system as a peripheral which can store data and perform specific operations on these, or a switching system as a buffer with real time processing and multiplexing capabilities. The architecture consists of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules. The design can operate at a data transfer speed of 622 Mbit/sec. Per flow queuing, implemented in shared memory, supports shaping and multiplexing operations on data, on a process/connection basis. The design is capable of multiplexing thousands of flows performing shaping according to a traffic profile for each flow. Traffic profiles could be either static according to negotiable network parameters or dynamic in applications, such as video transport, where a connection presents diversity in bandwidth allocation requirements. Dynamic update of traffic profiles involves real-time measurements and calculations of incoming packets. These operations are efficiently mapped in hardware/software components, inside the processing modules, implementing the respective algorithms. Performance trials of the design have indicated that the behaviour of the controller under heavy load improves with the use of the appropriate algorithms. The architecture embeds both the processing and the memory modules, thus producing a true system-on-a-chip solution
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ABSTRACT This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component... more
ABSTRACT This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true “system on a chip” solution
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The performance of a traffic shaper plays an important role in the overall performance of an ATM system because of the limitation that it imposes to the bandwidth allocation. An efficient scheduling process results in the improvement of... more
The performance of a traffic shaper plays an important role in the overall performance of an ATM system because of the limitation that it imposes to the bandwidth allocation. An efficient scheduling process results in the improvement of the system's performance. This paper presents four techniques, which enhance the performance of the traffic scheduling processes for ATM systems. The shaper uses a parallel calendar-based VLSI architecture to speed up the processes of searching, computing priorities and updating pointers. Each organization involves processing elements able to perform simple instructions and interconnected through a low cost interconnection scheme. The number of elements is proportional to the number k of priorities related to the traffic profiles of the ATM connections. Each organization presents an efficient solution to the problem of speeding up the computing the time-slots for transmitting ATM cells while keeping the required VLSI area small as well as simpli...
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Most network processors perform some kind of classification on the received packet stream, according to criteria set by the implemented networking application. Packet indexing is an integral part of the packet classification process.... more
Most network processors perform some kind of classification on the received packet stream, according to criteria set by the implemented networking application. Packet indexing is an integral part of the packet classification process. Indexing is considered as one of the most processor intensive part of network processing and is often supported by special hardware units. High performance Network processors usually rely upon Content Addressable Memories (CAMs) for the indexing of millions of packets per second into discrete "flow…
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Research Interests:
Giving the operator the ability to manage in- home devices greatly increases the potential of the cost-efficient provision of new profitable services. In this spirit, standardization undertaken by the DSL forum not only addresses remote... more
Giving the operator the ability to manage in- home devices greatly increases the potential of the cost-efficient provision of new profitable services. In this spirit, standardization undertaken by the DSL forum not only addresses remote management of the residential gateway but recently, also extends to in-house devices. We propose a solution that bridges remote management specified by CWMP with UPnP,
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XML technology is penetrating the network management in the IETF, UPnP, and DSL forum suite of standards and protocols. The advantages of XML are offered at the cost of long byte streams due to XML's inherently... more
XML technology is penetrating the network management in the IETF, UPnP, and DSL forum suite of standards and protocols. The advantages of XML are offered at the cost of long byte streams due to XML's inherently verbose nature. The increase in packet size for remote configuration and management can pose problems, if executed in a point-to-multipoint arrangement comprising one automatic configuration server and thousands of home gateways and multimedia devices. We investigate and exploit the repetitive nature of text patterns in typical XML documents as produced by the configuration and management tasks and as coded in SOAP RPCs. The solution mainly comes from application of the Lempel-Ziv compression algorithm, with minimal additions in the proposed DSL Forum standard. Numerical and experimental results support the applicability and advantages of the proposed approach and provide insight on how these are attributable to different layers of the employed protocol stack.
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... Fotis E. Andritsopoulos, Newton Bomeisel Cardoso, Gregory A. Doumenis, Yannis M. Mitsos, Lambros E. Sarakis E-mail: fandrit@telecom.ntua.gr, newton@cpqd ... Goertzel algorithm acts as an IIR filter that uses the feedback path to... more
... Fotis E. Andritsopoulos, Newton Bomeisel Cardoso, Gregory A. Doumenis, Yannis M. Mitsos, Lambros E. Sarakis E-mail: fandrit@telecom.ntua.gr, newton@cpqd ... Goertzel algorithm acts as an IIR filter that uses the feedback path to generate a very high Q bandpass fil-ter where ...
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Research Interests:
In multimedia applications, the stringent requirements for balancing transmission capacity, flexible service provisioning and cost reduction lead the manufactures to provide highly integrated System-on Chip (SoC) solutions. This paper... more
In multimedia applications, the stringent requirements for balancing transmission capacity, flexible service provisioning and cost reduction lead the manufactures to provide highly integrated System-on Chip (SoC) solutions. This paper analyzes the application of ...