Microelectronic Engineering 88 (2011) 1388–1391 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si0.45Ge0.55 pMOSFETs J. Franco a,b,⇑, B. Kaczer a, M. Toledano-Luque a,c, Ph. J. Roussel a, P. Hehenberger d, T. Grasser d, J. Mitard a, G. Eneman a,b,e, L. Witters a, T.Y. Hoffmann a, G. Groeseneken a,b a Imec, Kapeldreef 75, 3001 Leuven, Belgium ESAT, Katholieke Universiteit Leuven, Belgium Dpto. Física Aplicada III, Universitad Complutense Madrid, Spain d Technische Universität Wien, Austria e FWO-Vlaanderen, Belgium b c a r t i c l e i n f o Article history: Available online 30 March 2011 Keywords: NBTI SiGe Si Cap pMOSFET Passivation Reliability a b s t r a c t The negative bias temperature instability (NBTI) of nanoscaled Si0.45Ge0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (DVth) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average DVth step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction 2. Experimental We have recently shown that SiGe pMOSFETs with buried channel architecture can alleviate the NBTI issue for ultra-thin EOT devices [1]. A crucial impact of the Si cap thickness was found, with thinner Si caps significantly improving the reliability, possibly by reducing the interaction between channel carriers and dielectric defects thanks to a favorable Fermi level alignment shift [2,3]. This allowed us to demonstrate 6 Å EOT Si0.45Ge0.55 pFETs with a 10 year lifetime at operating VDD of 1 V [2]. However, those studies were performed on large area test devices, as customary for standard NBTI studies. Recent works have shown that as device geometries scale toward atomistic dimensions both the fresh device parameters and the parameter shifts during device operation become statistically distributed. At the same time, individual charge/discharge events become visible in the Vth transients, providing a new way to study oxide trap properties [4–7]. For these reasons, in this work we focus on the NBTI of nanoscaled Si0.45Ge0.55 pFETs, looking in particular into the impact of different Si cap thicknesses. Si0.45Ge0.55 pFETs with metallurgic length L  35 nm (drawn L = 70 nm) and width W = 90 nm were used in this study. The device gate stack (Fig. 1) consisted of a Si cap with three different thicknesses in the range of 0.65–2 nm (as grown), a SiO2 interfacial layer (0.8 nm), an HfO2 dielectric (1.8 nm), and a metal gate. More information on the process can be found in [8]. Up to 160 nominally identical devices were used for the statistical studies. ⇑ Corresponding author at: Imec, Kapeldreef 75, 3001 Leuven, Belgium. E-mail address: jacopo.franco@imec.be (J. Franco). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.065 3. Results and discussion A representative set of typical NBTI relaxation transients recorded with the extended measure-stress-measure (eMSM) technique [9] on nanoscaled SiGe devices is shown in Fig. 2a. As previously reported for Si devices [4,5], the total DVth observed after the same NBTI stress strongly varies from device to device. Single discharge events are visible, and the DVth step heights are exponentially distributed (Fig. 2b, complementary cumulative distribution function, CCDF  1-CDF) [5]. Several single discharge events are observed causing DVth as large as 20 mV. The step heights and the trap emission times are uncorrelated (not shown), as observed in [5] for the case of RTN, confirming that charge emission does not follow a simple elastic model [10]. While for large area devices the total DVth depends on the stress time (Fig. 3a) 1389 J. Franco et al. / Microelectronic Engineering 88 (2011) 1388–1391 MG HfO2 SiO2 IL Si cap 0.65-2nm (as grown) SiGe 55%, 5nm Si Fig. 1. Gate stack of the SiGe devices under test. Gate metallurgic length L was 35 nm (drawn L = 70 nm), while gate width was 90 nm. and on the stress gate overdrive voltage, for nanoscaled device the average number of discharge events per single stressed device is observed to follow similar dependences (Fig. 3b). A thinner Si cap on SiGe pFETs was found to strongly reduce the large area device DVth at fixed stress oxide electric field (Fig. 4a). In a similar way, a thinner Si cap causes a strong reduction of the average number of DVth steps (i.e. trapped charges) in nanoscaled devices (Fig. 4b, different stress conditions w.r.t. Fig. 4a). It is also worth noticing that the very small number of discharge events observed complicates the study, requiring large sample sets to get reliable statistics. 606 −ΔVth [mV] 1 70x90 nm2, 41x devices Si0.45Ge0.55/Si cap 2nm (a) T=25˚C tstress =132s VGstress=-2V Vth0=-0.14V 505 404 303 70x90 nm2, 41x devices Si0.45Ge0.55/Si cap 2nm T=25˚C tstress=132s VGstress=-2V Vth0=-0.14V 0.1 CCDF 707 Moreover, the CCDFs of the step heights for different Si cap thicknesses reveal that a thinner cap causes a reduction of the average step height (g) as shown in Fig. 5 (g = 3.9 mV for a 2 nm Si cap and g = 1.8 mV for a 0.65 nm Si cap). As shown in Fig. 6, this observation is confirmed at several stress equivalent oxide electric fields (Eox). Moreover, the observed g values are significantly lower w.r.t. the values previously observed for Si devices with similar gate stack (Si Ref. data from [5], g = 4.8–5.7 mV). Hence, the use of a thin Si cap on a SiGe channel reduces both the average number of steps and the average DVth step height after NBTI stress, confirming to be extremely beneficial also for the nanoscaled device reliability. A possible model to explain the experimental observations relies on the existence of a defect band in the dielectric at a narrow energy level, e.g. in the SiO2 at Ev_Si 0.4 eV, as observed in [10]. As depicted in Fig. 7, the Fermi level in the SiGe channel determines which part of the defect band will be accessible to channel holes. I.e. for a thin Si cap only a small part of the defect band located on the gate side of the dielectric is accessible, while the larger voltage drop on a thicker Si cap lowers the Fermi level making more defects accessible to channel holes. This interpretation qualitatively agrees with the higher average number of trapped charges observed for devices with a thicker Si cap. Moreover, the additionally accessed defects, being located nearer to the channel, shift the centroid (xt in Fig. 7) of the total trapped charge closer to the channel, explaining the observed higher g (Fig. 5) [11]. 0.01 202 − from [5] : = − 101 (b) 00 2 10-2 1 10-1 0 1 100 101 0.001 0 2 102 5 t relax [s] 10 15 20 25 Single Charge −ΔVth [mV] Fig. 2. (a) NBTI relaxation transients recorded on nanoscaled SiGe devices (measurement noise was filtered out), with visible single discharge events. (b) The complementary cumulative distribution function (CCDF  1-CDF) shows the DVths per single discharge event are exponentially distributed. VGstress-Vth0: -1.375 − ΔVth [V] -1.5 -1.625 -1.75 0.1 10 10x1 μm2 Si0.45Ge0.55/Si cap 2nm ∠ ≈ 0.13 (a) T=125˚C, tmeasure=2ms 0.01 1 10 100 t stress [s] 1000 10000 < # of steps per device > 1 (b) ∠≈ 1 VGstress: 0.1 0.01 T=25˚C Vth0=-0.14V 90x70 nm2 Si0.45Ge0.55/Si cap 2nm -1.5V -1.75V -2V -2.25V 0.1 0.13 1 10 100 1000 t stress [s] Fig. 3. (a) For large-area devices, the total DVth depends on the stress time and voltages. (b) For nanoscaled devices, the average number of discharge events (i.e. trapped charges per device) follows similar dependences. 1390 J. Franco et al. / Microelectronic Engineering 88 (2011) 1388–1391 100 Si cap: 10x1 μm2 2nm Si0.45Ge0.55 1nm − ΔVth [V] 0.1 0.65nm n = 4.5 ~ 5.7 0.01 T=125˚C, tstress=2000s, tmeasure=2ms (a) 0.001 6 10 14 < # of steps per device > 1 70x90 nm2 Si0.45Ge0.55 T=25˚C tstress=132s (b) 10 1 Si cap: 2nm 1nm 0.65nm 0.1 18 6 14 10 Eox [MV/cm] 18 Eox [MV/cm] Fig. 4. (a) The use of a thinner Si cap reduces the total DVth on a large area device (re-plotted from [1], field acceleration power-law exponents n  4.5 for the thickest cap, while n  5.7 for the thinnest cap) and (b) the average number of discharge events per device on nanoscaled SiGe pFETs (lines are guides to the eye here). Note: Eox  |VG Vth0|/Tinv here (Eox estimation from capacitance–voltage measurements was not possible due to the small area devices having Cox values below the detection limit of standard measurement equipment; Tinv = CET(Vth0 0.6 V)  EOT + 4 Å). As one can notice, very high oxide electric fields, up to 18 MV/cm, had to be applied in order to cause trap charging in SiGe devices with thinnest Si cap. This further proves the improved NBTI reliability of this technology. Furthermore, time dependent dielectric breakdown (TDDB) did not constitute a showstopper even at such high electric fields thanks to its area scaling. 6 70x90 nm2 Si0.45Ge0.55 5 T=25˚C tstress =132s VGstress=-2.25V 4 η [mV] CCDF 0.1 3 Si cap: 2nm 2 0.01 1nm Si cap: 1 0.65nm 2nm 0 T=25˚C tstress=132s Si ref. 0.65nm 0.001 70x90 nm2 Si0.45Ge0.55 tstress 1 0 10 20 5 10 30 Single Charge − ΔVth [mV] Fig. 5. The average DVth step height (g) is reduced when using a thinner Si cap. 15 20 Eox [MV/cm Fig. 6. Extracted average DVth step heights (g) as a function of the stress electric field for different Si cap thicknesses. Devices with a thinner Si cap show lower g, while in general SiGe devices show lower g w.r.t. Si Ref. data from [5]. E tSiO2 0 Si SiGe Si SiO2 HfO2 0 tSiO2/2 tSiO2 x MG Si SiGe Si SiO2 x HfO2 MG Fig. 7. Assuming the existence of a defect band (modeled as a Gaussian distribution of traps over the oxide energy bandgap) in the dielectric (e.g. in the SiO2 as observed in [10]) can explain the experimental observations. With thinner Si cap only a small part of the defect band located on the gate side can interact with channel holes, while for a thicker cap more defects become accessible on the channel side, explaining the higher average number of trapped charges per device and the higher g [11]. J. Franco et al. / Microelectronic Engineering 88 (2011) 1388–1391 1391 Finally the complementary cumulative distribution of the emission times observed for several stress times and voltages are plotted in Fig. 9 for different Si cap thickness. Interestingly the emission time distributions appear to be shifted toward lower values for thinner Si cap, suggesting a faster discharge of the trapped charges after stress removal, i.e. a faster initial relaxation. 4. Conclusion Fig. 8. Centroid of the accessible traps calculated for different values of the Fermi level in the channel. The model proposed in Fig. 7 qualitatively agrees with the experimental observation of the g dependency on the Si cap. 1 0.8 The NBTI reliability of nano-scaled Si0.45Ge0.55 pFETs was studied as a function of the Si cap thickness. Individual discharge events are visible in the DVth relaxation traces, with exponentially distributed step heights. The DVth step heights and the corresponding charge emission times were observed to be uncorrelated. The average number of discharge events follows the typical NBTI dependences on stress time and voltage observed for the total DVth on large area devices. The use of a thinner Si cap on SiGe was found to dramatically reduce the average number of discharge events and the average DVth step height (g), confirming this technology to be extremely promising also for nanoscaled device reliability. A simple model including a defect band in the dielectric can qualitatively explain the experimental observation, suggesting that fewer defects located on the gate side of the dielectric are accessible by the channel holes when reducing the Si cap thickness, thanks to a favorable Fermi energy alignment. CCDF Acknowledgements 0.6 Si cap: 2nm 1nm 0.65nm 0.4 0.2 70x90 nm2 Si0.45Ge0.55 T=25˚C, tstress=0.03s 132s VGstress=1.5V 2.25V 0 0.001 0.1 10 1000 t emission [s] Fig. 9. The CCDF of the emission times observed for several stress times and voltages and for different Si cap thickness are reminiscent of the relaxation traces observed on large area devices. For comparison, the inset shows a typical DVth relaxation trace for a 10  1 lm2 with a 2 nm Si cap. The emission time distributions appear to be shifted toward lower emission times for thinner Si cap, suggesting a faster discharge of the trapped charges after stress removal. A defect band is assumed with a Gaussian density of states (see the SiO2 layer and the Eq. in Fig. 7) with its mean value l centered at E = Ev_Si 0.4 eV at the Si/SiO2 interface and linearly changing with depth (with slope Eox) to account for the voltage drop in the dielectric. The centroid of the accessible traps (assuming all traps are charged after NBTI stress) can be numerically calculated for different values of the Fermi level in the channel. As shown in Fig. 8, this simple model qualitatively agrees with the experimental observation of the g dependency on the Si cap (shown in Fig. 6). This work was carried out as part of imec’s Industrial Affiliation Program funded by imec’s Core Partners. The imec pilot line and Amsimec are also acknowledged for their support. References [1] J. Franco, B. Kaczer, M. Cho, G. Eneman, T. Grasser, G. Groeseneken, Proc. IRPS (2010) 1082–1085. [2] J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanas’ev, T. Kauerauf, Ph.J. Roussel, M. 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