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Phase-locked loops (PLLs) exhibit a tradeoff between settling time and noise rejection, due to the fact that a low noise PLL requires a narrow bandwidth (BW) loop filter, which degrades settling time. However, the moments when fast settling or good noise rejection is required are clearly identified in a PLL, and this can be used to overcome this tradeoff. A

Abstract Two special calorimeters are foreseen for the instrumentation of the very forward region of the ILC detector, a luminometer designed to measure the rate of low angle Bhabha scattering events with a precision better than 10-3 and a low polar angle calorimeter, ...

... He showed me what was possible, setting a high standard for my final circuit test setup. ... also express my gratitude for the support received from past and present Woo-ley's group and Murmann's group students, especially Mohammad, Maryam, Rox-ana, Nasrin, Xinying, Sakshi ...

The BeamCal specifications for rate, gain, power dissipation, resolution and occupancy set unique challenges in the front-end and readout electronics design. In order to meet the required signal-to-noise ratio, a quasi-triangular weighting function is implemented using ...

ABSTRACT For certain applications, the offset voltage of the amplifiers represents a problem that must be addressed, since it may affect the transfer characteristics of the system. Offset memorization techniques allow to partially cancel the offset voltage either at the input or at the output of an amplifier, but their effectiveness is highly dependent on the amplifier gain. For this reason, these techniques do not result in a complete offset cancellation when used with low-gain amplifiers. In this work, a fully-differential offset-cancelling circuit based on offset memorization techniques is introduced along with its analysis and simulation results. Among the features of the proposed circuit are a configurable output common-mode voltage and a complete offset cancellation even when used with low-gain amplifiers.

ABSTRACT Engineering outreach in a developing country like Chile is a difficult challenge. Different reasons explain a sustained decrease in the number of students enrolling in engineering education in the past years, and a special effort is necessary to reverse this trend. Focusing on teamwork, the non-conventional undergraduate-level course described in this paper represents an opportunity for motivated students in a developing country to focus their abilities in engineering design. In order to make the course more attractive for students, the final project consisted of designing an autonomous robot to compete in a contest. This article reviews experiences associated with this course and the students' design teams over a five-year period. The course methodology is explained, and the results are summarised.

ABSTRACT With the adoption of new technology nodes q for analog circuits, different digital techniques have been designed to enhance their performance. Among the existing techniques, a promising approach is to adapt the circuit operation dynamically considering the application characteristics. In the field of analog-to-digital converters (ADCs), typically this approach is carried out by taking advantage of application-dependent signal properties, hence their use is limited. In this work, a digital assistance technique for power reduction in ADCs is presented. By defining a reduced valid range for the next sample based upon the maximum possible change of the input signal between samples, the proposed algorithm reduces the mean energy consumption per conversion in a variety of ADC architectures, regardless of the application.

ABSTRACT Charge amplifiers represent the standard solution to amplify signals from capacitive detectors in high energy physics experiments. In a typical front-end, the noise due to the charge amplifier, and particularly from its input transistor, limits the achievable resolution. The classic approach to attenuate noise effects in MOSFET charge amplifiers is to use the maximum power available, to use a minimum-length input device, and to establish the input transistor width in order to achieve the optimal capacitive matching at the input node. These conclusions, reached by analysis based on simple noise models, lead to sub-optimal results. In this work, a new approach on noise analysis for charge amplifiers based on an extension of the gm/ID methodology is presented. This method combines circuit equations and results from SPICE simulations, both valid for all operation regions and including all noise sources. The method, which allows to find the optimal operation point of the charge amplifier input device for maximum resolution, shows that the minimum device length is not necessarily the optimal, that flicker noise is responsible for the non-monotonic noise versus current function, and provides a deeper insight on the noise limits mechanism from an alternative and more design-oriented point of view.

ABSTRACT The BeamCal detector, one of the calorimeters in the forward region of the International Linear Collider detector, will serve three purposes: ensure hermeticity of the detector for small polar angles, reduce the backscattering from pairs into the detector center, and provide a low-latency signal for beam diagnostics. The BeamCal specifications in terms of noise suppression, signal charge, pulse rate and occupancy pose unique challenges in the front-end and readout electronics design. The Bean - BeamCal Instrumentation IC - is a 32-channel front-end and readout IC that will address the BeamCal instrumentation requirements. By employing switched-capacitor filters and a slow reset-release technique, the Bean will process the signal charge at the International Linear Collider pulse rate. Each channel will have a 10-bit successive approximation analog-to-digital converter and digital memory for readout purposes. The Bean will also feature a fast feedback adder, capable of providing an 8-bit, low-latency output for beam diagnostic purposes. This work presents the design and characterization of the Bean prototype, a 3-channel IC that proves the principle of operation described.

ABSTRACT Discrete-time filters represent a promising solution for pulse-processing in high-energy physics experiments due to their flexibility, reliability, and their capability to synthesize weighting functions with virtually any shape. One of the major concerns when designing one of these filters is to calculate the filter parameters that maximize the signal-to-noise ratio. The classic way to address this problem is to perform the noise analysis using a continuous-time domain approach based on the weighting function concept. However, when addressing the problem from an inadequate time domain, the analysis is not insightful and the resulting expressions are complex and difficult to use for design purposes. In this work, a mathematical framework for a design-oriented analysis of discrete-time filters in the discrete-time domain is presented. This analysis is based on treating the sampled noise as a discrete-time signal, which can be manipulated to obtain a closed-form expression for the front-end noise, suitable for computer automatic evaluation and filter optimization procedures. An example of the optimum filter formulation and computation is presented, in addition to several conclusions about optimum digital filtering.

ABSTRACT Metal-oxide-metal (MOM) capacitors represent an attractive alternative to metal-insulator-metal (MIM) capacitors in mixed-signal integrated circuits. Since they are made of metal lines, they can be integrated in standard CMOS processes, and tailored over a wide range of sizes. Mismatch data of MOM capacitors, however, is scarce and typically conservative. Presented is the design and the test results of a custom ADC that employs an array of 1024 MOM capacitors sized at 2 fF. Static performance metrics are presented and compared with those for an ADC based on MIM capacitors. Mismatch data is computed from the results.

ABSTRACT MOSFET models for deep submicron technologies involve accurate and complex equations not suitable for hand analysis. Although the gm/ID design-oriented approach has overcome this limitation by combining hand calculations with data obtained from SPICE simulations, it has not been systematically used for noise calculations, since the dependence of noise on this parameter is not direct. An attempt to express noise as a function of gm/ID is presented. By introducing the normalised noise concept, noise curves that depend solely on the device length and operation point can be obtained directly from SPICE simulations, and then used in the design flow. The main outcome is a simple design-oriented methodology for noise calculations that does not depend on equations for a specific technology or operating region, and that is easy to migrate among different technologies.