2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018
A low power base station analog TX chain and low noise PLL supporting all 3GPP R13/14 bands from ... more A low power base station analog TX chain and low noise PLL supporting all 3GPP R13/14 bands from 400MHz to 6GHz are implemented as part of a 4 transmit/receive and 2 feedback receive SOC in 28nm. With 600MHz of instantaneous bandwidth, the TX outputs −9dBm of LTE20 power with an ACLR of −68.6dBc and −159dBm/Hz noise floor at 2.6GHz while providing 40dB of gain control in 1dB steps. −60dBc of narrowband raw image rejection is obtained through analog quadrature correction. The PLL double sided integrated phase noise is −44dBc at 2.7GHz.
and low-cost VCO is discussed. The VCO uses on-chip schottky diode varactors and regular bondwire... more and low-cost VCO is discussed. The VCO uses on-chip schottky diode varactors and regular bondwires for its resonator. The VCO was implemented for the local oscillator (LO) of a GPS receiver. The VCO oscillates at 2.7-GHz which is double the LO. This frequency is divided to generate I and Q components of the LO. The core VCO uses MOS devices and can easily be integrated in any standard CMOS process with better performance. Regular bondwires used to form the resonator makes the design compact and cost-effective. Also the high-Q bondwire inductance helps reduce the power and phase noise. An automatic amplitude control (AAC) loop has been used to control the amplitude of the oscillation. The implemented VCO has a phase noise of-112dBc/Hz at an offset of 200kHz from the 2.7GHz carrier and the core consumes 2.5mA from a 3V supply. 1
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173), 2001
A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includ... more A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includes a 2.9 dB NF LNA, an image-reject mixer with 32 dB image rejection. The on-chip IF chain, which consists of a VGA, a 2nd mixer and filtering, has a maximum gain of 83 dB, a gain range of 45 dB and a 7 dB NF. A
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018
A low power base station analog TX chain and low noise PLL supporting all 3GPP R13/14 bands from ... more A low power base station analog TX chain and low noise PLL supporting all 3GPP R13/14 bands from 400MHz to 6GHz are implemented as part of a 4 transmit/receive and 2 feedback receive SOC in 28nm. With 600MHz of instantaneous bandwidth, the TX outputs −9dBm of LTE20 power with an ACLR of −68.6dBc and −159dBm/Hz noise floor at 2.6GHz while providing 40dB of gain control in 1dB steps. −60dBc of narrowband raw image rejection is obtained through analog quadrature correction. The PLL double sided integrated phase noise is −44dBc at 2.7GHz.
and low-cost VCO is discussed. The VCO uses on-chip schottky diode varactors and regular bondwire... more and low-cost VCO is discussed. The VCO uses on-chip schottky diode varactors and regular bondwires for its resonator. The VCO was implemented for the local oscillator (LO) of a GPS receiver. The VCO oscillates at 2.7-GHz which is double the LO. This frequency is divided to generate I and Q components of the LO. The core VCO uses MOS devices and can easily be integrated in any standard CMOS process with better performance. Regular bondwires used to form the resonator makes the design compact and cost-effective. Also the high-Q bondwire inductance helps reduce the power and phase noise. An automatic amplitude control (AAC) loop has been used to control the amplitude of the oscillation. The implemented VCO has a phase noise of-112dBc/Hz at an offset of 200kHz from the 2.7GHz carrier and the core consumes 2.5mA from a 3V supply. 1
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173), 2001
A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includ... more A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includes a 2.9 dB NF LNA, an image-reject mixer with 32 dB image rejection. The on-chip IF chain, which consists of a VGA, a 2nd mixer and filtering, has a maximum gain of 83 dB, a gain range of 45 dB and a 7 dB NF. A
2011 IEEE International Solid-State Circuits Conference, 2011
ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applica... more ABSTRACT This forum will cover present and future transmitters in wireless infrastructure applications, like base stations for cellular mobile communication. Future digitized transmitter architectures will most likely be based upon the use of advanced RF DACs or ultra high speed DACs in combination with up conversion techniques. These digital transmitter architectures need flexible (re-configurable) power amplifiers which make use of advanced techniques like multi-way Doherty or envelope tracking. Enhanced linearization techniques need to be applied in the transmitter to cope with the stringent linearity demands, while advanced calibration techniques and other design techniques will be needed to overcome circuit block impairments.
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