Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of first-time users in the developing countries has spurred development of single-chip 2G radios that integrate an RF transceiver with a digi-tal... more
Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of first-time users in the developing countries has spurred development of single-chip 2G radios that integrate an RF transceiver with a digi-tal baseband (DBB) processor in scaled ...
Publication Date: 2008
Publication Name: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process based on the digital RF Processor (DRPtrade) technology. This chip integrates all functions from physical layer to the protocol stack and... more
In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process based on the digital RF Processor (DRPtrade) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly
Publication Date: 2009
Publication Name: 2009 IEEE Radio Frequency Integrated Circuits Symposium
AbstractWe present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm... more
AbstractWe present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses ...
Publication Date: 2005
Publication Name: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
We present a discrete time Bluetooth receive architecture imple-mented in a 130nm digital CMOS process without any process enhancements. The presented design integrates the digital baseband (DBB), RF, memory, power management and RF... more
We present a discrete time Bluetooth receive architecture imple-mented in a 130nm digital CMOS process without any process enhancements. The presented design integrates the digital baseband (DBB), RF, memory, power management and RF built-in self test (RFBIST) in an SOC that ...
