2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004
This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using... more This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin single crystal layers of Ge [001] have been successfully transferred via oxide to oxide bonding or by Ge to oxide bonding, onto 100 mm and 200 mm Si substrates.
Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the... more Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO2/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)
ABSTRACT Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-pa... more ABSTRACT Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-passivation are studied at low temperature. The impact of the starting Ge material and N-type channel doping on threshold voltage is examined. As there is no evidence of a background doping in Ge films, the typical parasitic conduction and threshold voltage shift in p-channel GeOI MOSFETs are due to interface states. An extended model predicting the threshold voltage temperature dependence in GeOI transistors is proposed.
We demonstrate for the first time 70nm gate length TiN/HfO2 pMOSFETs on 200mm GeOI wafers, with e... more We demonstrate for the first time 70nm gate length TiN/HfO2 pMOSFETs on 200mm GeOI wafers, with excellent performance: ION=260μA/μm and IOFF=500nA/μm @ Vd=−1.0V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. IOFF trade-off for Ge or GeOI devices: CV/I=4.4ps, IOFF=500nA/μm @ Vd=−1V. Moreover, based on fine electrical characterizations (μ, Dit,
ABSTRACT We have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates usi... more ABSTRACT We have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of 'mounds' and a perpendicular cross-hatch were obtained on nominal surfaces. On 6° off surfaces, three sets of lines were obtained on top of the 'mounds': one along the 1 1 0 direction perpendicular to the misorientation direction and the other two at ~4.5° on each side of the 1 1 0 direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 µm thick nominal and 6° off Ge layers. Those slightly tensily strained Ge layers (R ~ 104%) were characterized by 5 × 107 cm−2 (as-grown layers) −107 cm−2 (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 °C/650 °C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An ~5 Å thick SiGe interfacial layer is self-limitedly grown at 550 °C and then thickened at 650 °C (5 Å min−1) thanks to SiH2Cl2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 Å Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 Å thick Si layer).
ABSTRACT The problematics of contacts optimization on germanium metal-oxide-semiconductor field-e... more ABSTRACT The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of for electrons and for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.
As layer transfer techniques have been notably improved in the past years, lithium niobate (LiNbO... more As layer transfer techniques have been notably improved in the past years, lithium niobate (LiNbO3) appears as a candidate for the next generation of ultrawide band radio frequency (rf) filters. Depending on the crystalline orientation, LiNbO3 can achieve electromechanical coupling factors Kt2 more than six times larger than those of sputtered aluminum nitride films. In this letter, a process based on direct bonding, grinding, polishing, and deep reactive ion etching is proposed to fabricate a single crystal LiNbO3 film bulk acoustic resonator. From the fabricated test vehicles, Kt2 of 43% is measured confirming the values predicted by theoretical computations.
ABSTRACT In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using eith... more ABSTRACT In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management.We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200nm to 7000nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5µm thick diamond layer could be reduced from 50 to 3nm RMS and down to 1.5nm RMS for a thin 200nm layer.In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC.Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70nm) of 50mm diameter onto a 140nm thick diamond BOX layer has been transferred on 200mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004
This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using... more This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin single crystal layers of Ge [001] have been successfully transferred via oxide to oxide bonding or by Ge to oxide bonding, onto 100 mm and 200 mm Si substrates.
Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the... more Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO2/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)
ABSTRACT Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-pa... more ABSTRACT Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-passivation are studied at low temperature. The impact of the starting Ge material and N-type channel doping on threshold voltage is examined. As there is no evidence of a background doping in Ge films, the typical parasitic conduction and threshold voltage shift in p-channel GeOI MOSFETs are due to interface states. An extended model predicting the threshold voltage temperature dependence in GeOI transistors is proposed.
We demonstrate for the first time 70nm gate length TiN/HfO2 pMOSFETs on 200mm GeOI wafers, with e... more We demonstrate for the first time 70nm gate length TiN/HfO2 pMOSFETs on 200mm GeOI wafers, with excellent performance: ION=260μA/μm and IOFF=500nA/μm @ Vd=−1.0V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. IOFF trade-off for Ge or GeOI devices: CV/I=4.4ps, IOFF=500nA/μm @ Vd=−1V. Moreover, based on fine electrical characterizations (μ, Dit,
ABSTRACT We have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates usi... more ABSTRACT We have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of 'mounds' and a perpendicular cross-hatch were obtained on nominal surfaces. On 6° off surfaces, three sets of lines were obtained on top of the 'mounds': one along the 1 1 0 direction perpendicular to the misorientation direction and the other two at ~4.5° on each side of the 1 1 0 direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 µm thick nominal and 6° off Ge layers. Those slightly tensily strained Ge layers (R ~ 104%) were characterized by 5 × 107 cm−2 (as-grown layers) −107 cm−2 (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 °C/650 °C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An ~5 Å thick SiGe interfacial layer is self-limitedly grown at 550 °C and then thickened at 650 °C (5 Å min−1) thanks to SiH2Cl2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 Å Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 Å thick Si layer).
ABSTRACT The problematics of contacts optimization on germanium metal-oxide-semiconductor field-e... more ABSTRACT The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of for electrons and for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.
As layer transfer techniques have been notably improved in the past years, lithium niobate (LiNbO... more As layer transfer techniques have been notably improved in the past years, lithium niobate (LiNbO3) appears as a candidate for the next generation of ultrawide band radio frequency (rf) filters. Depending on the crystalline orientation, LiNbO3 can achieve electromechanical coupling factors Kt2 more than six times larger than those of sputtered aluminum nitride films. In this letter, a process based on direct bonding, grinding, polishing, and deep reactive ion etching is proposed to fabricate a single crystal LiNbO3 film bulk acoustic resonator. From the fabricated test vehicles, Kt2 of 43% is measured confirming the values predicted by theoretical computations.
ABSTRACT In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using eith... more ABSTRACT In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management.We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200nm to 7000nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5µm thick diamond layer could be reduced from 50 to 3nm RMS and down to 1.5nm RMS for a thin 200nm layer.In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC.Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70nm) of 50mm diameter onto a 140nm thick diamond BOX layer has been transferred on 200mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.
Uploads
Papers by L. Clavelier