Shrikant Honade

Power is the amount to function or generating or shelling out energy. This means that, it is a way of measuring how fast a function can be carried out. It means it is an important parameter. So to have less power consumption, this work is implemented using VLSI technology. This paper presents the design and simulation of VLSI based low power fractional- N Phase locked loop frequency synthesizer. This phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. For improving the performance of fractional-N phase locked loop, Loop filter and sigma-delta modulator are the most important components. The loop filter bandwidth limits the speed of switching time between the synthesized frequencies. The periodic operation of dual modulus divider introduces phase noise in the PLL. To eliminate this phase noise, the digital sigma-delta modulator is used which generates a random integer number with an average equal to desired fractional ratio a...

Adaptive signal processing is extensively used as an area of research from few decades. There are various kinds of adaptive filtering algorithms are available in the literature which are used for different purposes. The work presented in this paper focused mainly on the performance analysis of various versions of most popular LMS (Least Mean Square) adaptive filtering algorithm when it is operated in unknown environment and deciding which algorithm has better performance in terms of minimum mean square error (MSE). From, the experimental results, it is observed that, when a same random input, random noise and desired response are considered for the different algorithms, with variable step size parameter and variable no. of filter taps, it very difficult to form a concrete decision on it, but in broader sense we can say that the performance of LMS sign sign algorithm for M = 2 and NLMS/Complex NLMS algorithm for higher value of M is found to be better in terms of mean square value of error when operated in an unknown situation.

Now a day, optimization is one of the emerging and fastest growing fields in the area of Very Large Scale Integrated Circuits (VLSI). In real time environment, there are certain situations where the apriori information about the statistics of signal to be processed is not known completely, so in such situations adaptive filters are preferred. This paper deals with the survey of design of adaptive filters using low power adder and multipliers using Very Large Scale Integrated Circuits. The evaluation of power, area and speed for different types of adders and multipliers will be taken into account and the adaptive filter will be designed with efficient combination of adders and multipliers for low power and high speed applications. Various tools will be used for the design of the adaptive filters. The performance analysis of the proposed method will also be done in terms of speed, area, power consumption and hardware requirements.

power has become one of the most important parameter in various communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. This paper presents the design and simulation of VLSI based low power fractional- N Phase locked loop frequency synthesizer for Bluetooth application. Among variety of frequency synthesis techniques , phase locked loop (PLL) represents the dominant method in the wireless communications industry. PLL, like most wireless communication technologies, is relatively new and has matured only in the last decade. This phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. For improving the performance of fractional-N phase locked loop, Loop filter and Sigma-Delta modulator are the most important factors. The loop filter bandwidth limits the speed of switching time between the synthesized frequencies. The Periodic operation of dual modulus divider introduces phase noise in...