Computer Science And Engineering

Presenting novel designs for a Ripple Carry Adder, a Subtractor, and a Pipelined Array Multiplier using the Five-input Majority Gate (MAJ5) in Quantum-dor Cellular Automata (QCA). These designs are then used to implement the Fast Fourier Transform (FFT) Algorithm. The FFT implementation was previously introduced in 2012. However, it suffered from inefficiencies in terms of both area and speed, which are essential features for the aforementioned algorithm. The new designs are designed, optimized, and simulated using QCADesigner. It is shown that they indeed achieve higher levels of compactness and speed, due largely to the utilization of MAJ5, in addition to a new wire-crossing scheme suggested by another group. These building blocks are then used to optimize the FFT QCA implementation.

—In order to efficiently support the Machine-to-Machine (M2M) and Internet of Things (IoT) applications, a new amendment for the Wi-Fi standard known as IEEE 802.11ah is introduced. In 802.11ah (or Wi-Fi HaLow), several enhanced MAC features are added in order to provide scalability for a large number of stations, increase the range of operation, while at the same time reduce the energy consumption compared to the existing Wi-Fi standards. In this paper, a Verilog RTL implementation of the new standard is presented. It is suitable for IoT, M2M, V2V (Vehicle-to-Vehicle) applications, and smart grids that require long battery life and long range reliability. Software simulations using Xilinx Vivado are also provided to verify the design. The design is then synthesized using the same tool, and performance, power, and area are reported.

—Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with more emphasis on programmability, flexibility, portability, and energy efficiency, in cellular, WiFi, and M2M communication. Consequently, SDR has earned a lot of attention and is of great significance to both academia and industry. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. This paper is a survey of the state-of-the-art SDR platforms in the context of wireless communication protocols. We offer an overview of SDR architecture and its basic components, then discuss the significant design trends and development tools. In addition, we highlight key contrasts between SDR architectures with regards to energy, computing power, and area, based on a set of metrics. We also review existing SDR platforms and present an analytical comparison as a guide to developers. Finally, we recognize a few of the related research topics and summarize potential solutions.

While a general strategy for designing combinational circuits exists, little work has been done on sequential circuits using nanotechnology. This is due to the logic used to realize them, and hence designing circuits can be extremely complex. In this paper, the realization of sequential circuits in nanotechnology using threshold logic is addressed, and a novel methodology for realizing threshold logic-based state machines is proposed. This methodology presents a systematic approach to solve the issue of synchronicity with minimal hardware cost.

Software-defined radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with a greater emphasis on programmability, flexibility, portability, and energy efficiency in cellular, WiFi, and M2M communication. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. In this paper, we discuss the HW/SW co-design approach for SDR platforms in the context of wireless communication protocols. We offer a partitioning method of heterogeneous SDR architectures and then discuss the use of Xilinx SDSoC tool for accurate and effective system profiling. To demonstrate our method, we use IEEE 802.11a wireless standard to implement on the Xilinx Zynq-7000 System-on-Chip (SoC). We are able to achieve a significant speedup of 8.7 Â, compared to a software-only implementation. We also achieved a factor of 1.07 Â improvement in terms of power consumption, compared to a hardware-only implementation. Optimization techniques are also adopted for further speedups, and their effectiveness enable us to achieve a speedup of 1.08 Â, compared to a hardware-only implementation.

The blockchain space has seen tremendous innovation and advancement, in the last few years with an explosion of functionality and use cases.  However, several challenges naturally arise from the nature of these distributed systems - energy efficiency, privacy, and scalability challenges due to the computational resources required to generate, validate, and store the cryptographic proofs that provide immutable security.  New applications of recursive proof composition offer paradigmatic improvements that effectively address these challenges.
This paper addresses the practical implementation of these theoretical advances.

We demonstrate how HW/SW co-design methods can be algorithmically applied to identify practical hardware optimizations for the cryptographic verification of these zero-knowledge proofs, using Halo as an example.
We offer a partitioning methodology of blockchain operations and then discuss the use of the Binary Particle Swarm Optimization (BPSO) algorithm for systemic optimization.  To demonstrate our methodology, we implement the Halo algorithm on the Xilinx Zynq-7000 System-on-Chip (SoC).  We successfully achieve a considerable speedup of 2.2x, compared to a software-only implementation on a CPU.

Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with a greater emphasis on programmability, flexibility, portability, and energy efficiency in cellular, WiFi, and M2M communication. Consequently, SDR has earned a lot of attention and is of great significance to both academia and industry. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. This paper is a survey of the state-of-the-art SDR platforms in the context of wireless communication protocols. We offer an overview of SDR architecture and its basic components, and then discuss the significant design trends and development tools. In addition, we highlight key contrasts between SDR a...

People display regularities in almost everything they do. This paper proposes characteristics of an idealized algorithm that, when applied to sequences of user actions, would allow a user interface to adapt over time to an individual's pattern of use. We describe a simple predictive method with these characteristics and show its predictive accuracy on a large dataset of UNIX commands to be at least as good as others that have been considered, while using fewer computational and memory resources.