Christian Mayr

Resistive switching devices are considered as one of the most promising candidates for the next generation memories and nonvolatile logic applications. In this paper, BiFeO3:Ti/BiFeO3 (BFTO/BFO) bilayer structures with optimized BFTO/BFO thickness ratio which show symmetric, bipolar, and nonvolatile resistive switching with good retention and endurance performance, are presented. The resistive switching mechanism is understood by a model of flexible top and bottom Schottky-like barrier heights in the BFTO/BFO bilayer structures. The resistive switching at both positive and negative bias make it possible to use both polarities of reading bias to simultaneously program and store all 16 Boolean logic functions into a single cell of a BFTO/BFO bilayer structure in three logic cycles.

Low-energy Ar+ ion irradiation has been applied to an Au/BiFeO3/Pt capacitor structure before deposition of the Au top electrode. The irradiated thin film exhibits multilevel resistive switching (RS) without detrimental resistance degradation, which makes the intermediate resistance states more distinguishable, as compared with the nonirradiated thin film. The stabilization of resistance states after irradiation is discussed based on the analysis of the conduction mechanism during the RS, which was investigated by means of temperature-dependent current-voltage measurement from room temperature to 423 K.

For neuromorphic ICs, the implemented synaptic dynamics play an important role in the complexity achievable when running networks on the overall IC. One of these ingredients for realistic dynamics are conductance-based synapses, which in contrast to current-based synapses let a neuron adapt in various ways to its input characteristics. Another ingredient is classical neuronal spike-frequency adaptation. Both are usually realized in fully-analog subthreshold circuits, making them hard to port to modern sub-100nm technologies. In contrast, we present a compact switched-capacitor (SC) model of a conductance-based synapse that can be widely configured to accurately depict e.g. NMDA, GABA or AMPA type synapses. The SC approach is inherently easy to port between technologies and its digital part benefits fully from technology scaling. We show how this synapse circuit can also be utilized to endow a neuron with spike-frequency adaptation (SFA).

Chua [IEEE Trans. Circuit Theory 18, 507–519 (1971)] predicted rather simple charge-flux curves for active and passive memristors (short for memory resistors) and presented active memristor circuit realizations already in the 1970 s. The first passive memristor has been presented in 2008 [D. B. Strukov, G. S. Snider, and D. R. Williams, Nature (London) 453, 80–83 (2008)]. Typically, memristors are traced in complicated hysteretic current-voltage curves. Therefore, the true essence of many new memristive devices has not been discovered so far. Here, we give a practical guide on how to use normalized charge-flux curves for the prediction of hysteretic current-voltage characteristics of memristors. In the case of memristive BiFeO3 thin film capacitor structures, the normalized charge-flux curves superimpose for different numbers of measurement points Ns and a different measurement time per measurement point Ts. Such normalized charge-flux curves can be used for the prediction of current-voltage characteristics for input signals with arbitrarily chosen Ns and Ts.

We present an aliasing-free variable gain Delta Sigma Modulator (DSM). The variable gain of the 2-1-1 MASH architecture DSM is carried out by using additional sampling capacitors. This feedforward gain adjustment offers better S2-1-1 MASH architecture DSMNR performance than feedback gain adjustments discussed in the literature, since the internal states of the modulator loop are driven at full signal swing. To eliminate the need for an analog anti-aliasing filter, a decimation filter with a sharp cutoff is employed in the reconstruction of the analog signal. The design is carried out in a 0.6 μm CMOS technology. Measurement & implementation results for the above concepts compare favorably with similar designs in recent literature.

In this paper we present a novel switched-capacitor implementation of short-term synaptic dynamics with simultaneous depression and facilitation. The developed circuit model is a modified version of a model of neurotransmitter release derived from biological measurements. Despite the simplicity of the circuit the rich dynamics of the original model can be delivered. By completely relying on SC techniques for all calculations, our circuit is significantly less sensitive to process variations and easier to calibrate than commonly employed subthreshold circuits. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Functionality and robustness of the circuit are verified by simulations and comparisons to the original model.

The computational function of neural networks is thought to depend primarily on the learning/plasticity function carried out at the synapse. Neuromorphic circuit realizations have taken this into account by implementing a variety of synaptical processing functions, with most recent synapse circuits replicating some form of Spike Time Dependent Plasticity (STDP). However, STDP is being challenged by older rate-dependent learning rules as well as by biological experiments exhibiting more complex timing rules (e.g. spike triplets) as well as simultaneous rate- and timing dependent plasticity. In this paper, we present a circuit realization of a plasticity rule based on the postsynaptic neuron potential as well as the transmission profile of the presynaptic spike. To the best of our knowledge, this is the first circuit realization of synaptical behaviour which moves significantly beyond STDP, replicating the triplet experiments of Froemke and Dan, the combined timing and rate experiments of Sjoestroem et al., as well as conventional BCM behaviour.

The Bienenstock-Cooper-Munroe (BCM) rule is one of the best-established learning formalisms for neural tissue. However, as it is based on pulse rates, it can not account for recent spike-based experimental protocols that have led to spike timing dependent plasticity (STDP) rules. At the same time, STDP is being challenged by experiments exhibiting more complex timing rules (e.g. triplets) as well as simultaneous rate- and timing dependent plasticity. We derive a formulation of the BCM rule which is based on the instantaneous postsynaptic membrane potential as well as the transmission profile of the presynaptic spike. While this rule is neither directly rate nor timing based, it can replicate BCM, conventional STDP and spike triplet experimental data, despite incorporating only two state variables. Moreover, these behaviors can be replicated with the same set of only four free parameters, avoiding the overfitting problem of more involved plasticity rules.

Neuromorphic circuits try to replicate aspects of the information processing in neural tissue. Historically, this has often meant some kind of long-term learning function which slowly adjusts the weight of a synapse to achieve a certain target network function. Recently, short-term dynamics at the synapse have also gained significant attention due to their role in dynamic and temporal information processing. However, only very few neuromorphic circuits have incorporated short term dynamics, with still fewer of these implementations being biologically realistic. We derive a circuit for biologically relevant short term dynamics, showing its accuracy with respect to biological measurements. Since this circuit significantly increases the overall complexity of the synapse, a direct integration in the synapse would be prohibitive. Thus, in addition to the short term dynamics, we also present a novel configurable topology for the neurons and synapses on chip which achieves a compact and flexible overall design while still augmenting all synapses with the new short term dynamics.

For event based routing using global timestamps a sorting and buffering component is required. This work describes the implementation of a priority queue algorithm applying a binary heap structure, which efficiently combines the data storage and the reordering according to the data timestamp. For operation only two main functionalities are required, which insert and retrieve elements while assuring the heap property. The developed algorithmic enhancements offer significant optimisation of the runtime behaviour compared to standard heap algorithms and allow the usage of SRAM as storage memory, which provides substantial reduction of silicon area. The algorithms are implemented in UMC 180 nm technology and integrated into a large-scale VLSI routing system.