APPLICATION OF ALPHA POWER LAW MODELS TO PLL DESIGN METHODOLOGY B. Suresh1, V.Visvanathan1, R.S. Krishnan1 and H.S. Jamadagni2 1. ASIC Product Development, Texas Instruments Inc, Bangalore, India. 2.Professor, Centre for Electronic Design and Technology, Indian Institute of Science, Bangalore, India. ABSTRACT Designing, verifying and characterizing PLLs across Process, Voltage and Temperature (PVT) variations takes large amounts of time, often resulting in empirical design approaches. Behavioral modeling of PLLs has been presented in literature and is also supported to varying degrees by EDA tools. However these approaches are either too simplistic or wanting in their ability to explore the PVT space. We present a behavioral model approach for Phase Locked Loops using alpha power law behavioral models, which quickly allow the designer to examine design tradeoffs during early development phase. Self Biased PLLs were used as a vehicle in this work.. Behavioral models for each of the PLL sub blocks were developed using Analog description language. The proposed approach provides a speed-up of more than 75X with respect to SPICE with less than 10% error on a PLL in a 130nm CMOS process at 900Mhz. 1. INTRODUCTION Almost every ASIC consists of a clock generation circuit, which is typically implemented using a Phase locked loop (PLL). While the translation of specifications to digital circuits is automated by the presence of mature design/verification tools & ready-to-use libraries with a rich set of functions/characteristics, analog design automation has been limited and will still be, due to the need for designing to second order performance specifications. Design of PLLs requires the involvement of skilled designers who make use of past experience to define architectures, and optimize circuits for performance. Due to large simulation times involved in ensuring conformance to specifications across PVT, empirical or worst case design methodologies, that don’t fully explore the design space for trade-offs have to be resorted to [1]. The problem is compounded by the peculiarities of an ASIC environment: (a) Package, Interconnects, Power/Ground Bussing (b) Noise generation by digital circuits and their propagation through substrate (c) Inadequate technology characterization models for Analog Transistors, typical of deep sub-micron technologies. These effects vary from one design to another, making it further important to fully understand the design space. This necessitates a methodology that would enable the designer to develop the most optimal PLL, without increasing design cycle time. The methodology should allow a bottom-up verification that accounts for parasitic. In Section 2, various behavioral models and their limitations are presented. Section 3 outlines the proposed PLL design methodology using behavioral models. This model is applied to develop a behavioral model for a differential delay buffer. This differential delay buffer is used to construct a 4-stage VCO and its performance Vs SPICE is compared in section 5. Closed loop PLL simulation was performed for a self-bias PLL design [14] using the alpha power law behavioral model. The performance metrics are compared against those from BSIM3 model in section 6. 2. BEHAVIOURAL MODEL SURVEY Time taken to reduce the PLL simulation run time is a known research problem. There are various ways in which this problem can be solved and they can be broadly classified into three different categories. They are • Macro-modeling Based approach • Improved Simulation Techniques • Behavioral Modeling Based approach. Macro Modeling Based Approach In the macro modeling based approach, the PLL is abstracted into much simpler form; typically circuit components such as capacitors, controlled sources and resistors. Mark Sitkowski et.al [2,3] proposed modeling phase locked loop in terms of simple linear elements. Accordingly, oscillators are implemented using a technique called "infinite ringing" i.e. a tuned circuit formed by inductor and capacitor is set into oscillation; it will ring at its oscillating frequency, without the need for any positive feedback. Similarly error detector is implemented as linear voltage controlled voltage source with the polynomial transfer function. This model is novel, simple and easy to implement in any SPICE simulator. However, it is difficult to model second order effects like process, voltage and temperature variation on PLL performance. This macro-model will not model phase noise or jitter well. Improved Simulation Techniques Numerical simulation algorithms have been analyzed in [4-5] for faster PLL simulation run-times. The authors of [4] discuss two schemes; Interpolation method and Iterative method to solve the timing of switching events. They implemented these two schemes to simulate Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE the phase/delay locked systems. However, authors do not compare the PLL performance metrics simulated using SPICE simulator with the proposed algorithm. Authors in [5] proposed a method for the numerical analysis of charge pump PLL in time domain using behavioral modeling of non-linear elements. Authors do not provide comparative results against SPICE. Behavioral Modeling Based approach In behavioral modeling, circuit/system behavior is represented in-terms of high-level functions, which are independent of circuits. Behavioral simulation is performed using these models to quickly evaluate the system performance. These behavioral models can be defined in terms of 1) state-space models 2) algebraic expressions 3) mixed algebraic and differential equations. The challenge in this behavioral modeling approach is to model all the second-order effects such as voltage and temperature variation associated with the system. In PLL behavioral modeling, VCO behavioral model is an important component, which needs to be modeled accurately to evaluate overall PLL performance. There are different VCO behavioral models discussed in the literature. In one implementation, VCO frequency is represented by a simple linear function of control voltage [6,7], as shown in equation (1). f = k (V c ) + c (1) Where Vc is the VCO control voltage and f is the frequency, k and c are constants. VCO can also be represented as a quadratic expression [8] of the control voltage as shown in equation (2). (2) f = a V + b V + c 2 c c a, b & c are constants, calculated from VCO characterization In these implementations, VCO circuit is characterized to determine the constants a, b and c. These constants (a, b, c and Kvco) vary over process, voltage and temperature. While these classes of VCO behavioral models are easier to implement, they does not lend itself to modeling parasitic effects and PVT effects on jitter. Edward Liu et.,al [9] came up with a two stage non-linear VCO behavioral representation. The first stage is an ideal VCO stage whose output frequency is a linear function of input control voltage. Second stage consists of nonlinear Dynamic element whose output contains fundamental and harmonic frequencies. When such an ideal input is fed to the non-linear dynamic stage, the output will be Volterra kernels of stage 2. The VCO netlist at transistor level is needed to extract the required parameters. This means larger run times. Further, jitter, loop bandwidth and damping factor simulations are not clearly explained and no comparison is made between the simulation results and measurements. Georges Gielen et.al [11] came up with the behavioral VCO model in frequency domain (s-domain). This VCO model is a linear representation in frequency domain and does not model the harmonic distortions. The following are the issues, which need to be addressed in the behavioral models. • models either require schematics or characterized data to develop the behavioral representation. • models abstract the VCO at the functional level and hence it is very difficult to take care of process, temperature and voltage effects. • VCO is modeled as integral of control voltage, which represents an average over time. Therefore VCO output phase cannot follow any small instantaneous variations on the control voltage, which is an important source for jitter. Hence these models are used at the initial design stage to get a quick estimate of system performance where accuracy is not an important factor. Non-linear behavioral modeling [12] for delay locked and phase locked loops was introduced by Lin Wu .et .al. The authors proposed modeling the VCO by its individual components rather than VCO as a whole. VCO is implemented as a delay chain connected as a loop. Each of the delay elements is implemented from an inverter to the complex differential delay element. Each delay element is modeled as a RC time constant where R is typically implemented as a voltage controlled resistance. Capacitance C is calculated from the parasitic and drain capacitance of the current stage and the gate capacitance of the next delay element. These delay models are then used to construct the VCO behavioral model. Behavioral model discussed in this paper is different from previous behavioral models, in that it represents the VCO by modeling individual delay elements, whereas previous models abstract the VCO behavior as a whole. Our work also models some of the second order effects such as voltage and temperature variations because of its inherent delay model. 3. PROPOSED PLL METHODOLOGY The Proposed PLL design methodology is shown in Figure1. The design methodology should support the following: • • Usage of behavioral models with different levels of abstraction for the individual PLL components. This will allow use of functional models to transistor level models depending upon accuracy and run time tradeoff. Bottom-up verification i.e., extraction of block level parameters (e.g. VCO gain) from their layouts for use in behavioural models. Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE • explore the process, voltage and temperature (PVT) space. PLL SPECS CAPTURE INDIVIDUAL BLOCK DESIGN VCO CHARGE PUMP PFD DIVIDER BIAS GEN Where Vth is the threshold voltage, α is the velocity saturation index, Vd0 is the drain saturation voltage at Vgs = Vdd and Id0 is the drain current at Vgs = Vds = Vdd In order to calculate the Vth and α, pick the three measured points that need to be fitted from Vgs-Id characteristics. Suppose the three points are (Vg1, Id1) (Vg2, Id2) and (Vg3, Id3) then § I · § V −V · § I · §V −V · f (Vth ) = log¨¨ D1 ¸¸ log¨¨ g 2 th ¸¸ − log¨¨ D 2 ¸¸ log¨¨ g1 th ¸¸ = 0 © I D 2 ¹ © Vg 3 − Vth ¹ © I D 3 ¹ © Vg 2 − Vth ¹ α = CLOSED LOOP BEHAVIOURAL MODEL SIMULATION (Models with different Levels of Abstraction) CLOSED LOOP SPICE SIMULATION FIG 1: PLL DESIGN METHODOLOGY Traditionally, designers use closed loop spice simulations to fine tune individual blocks across process, voltage and temperature (PVT), which often take large amount of design time. In this proposed methodology, behavioural model is used for each individual block for faster closed loop simulations. Depending upon accuracy needs, appropriate model abstraction is used for closed loop simulations. This behavioural model approach allows the user to examine the PLL performance across PVT and try out different design trade-offs to arrive at an optimal design. Moreover this methodology allows for mix-andmatch of individual blocks with different levels of abstaction for fast closed loop simulations with good accuracy. This behavioural model also supports back annotation of layout parasitics for post-layout verification. 4. (V gs <= V th ) (cutoff Region) 0 ' §I · Id = ¨ d 0 ' ¸V DS V DS < V D' 0 ( Linear Region) V © d0 ¹ I D' 0 V DS ≥ V D' 0 (Saturation Region) where V ' D0 I )) In figure 2, alpha power law models the saturation region as a constant current. However the linear region of the I-V curve is approximated with the slope of (Id0’/Vd0’). This model fails to reproduce the characteristics of the region near and below the threshold voltage of the MOS transistor. So it is logical to use this alpha power model in applications where MOS transistor is mostly operated in the saturation region like in current mirrors, charge pumps and voltage controlled oscillators etc. 1.025/0.175 NCH, Nom, 25, 1.2V ALPHA POWER LAW MODELS Traditionally all the MOS transistors use the BSIM3/BSIM4 models for spice simulation, which accurately models the transistor parameters. Sukurai et. al.[13] came up with simple empirical formulae, which model the I-V curves of the MOS transistors. The I-V curves of the MOS transistor in alpha power model is given by ' d0 log (I D 1 I D 2 ) log ((V g 1 − V th ) (V g 2 − V th § V − V th = I D 0 ¨¨ gs © V DD − V th § V − V th = V D 0 ¨¨ gs © V DD − V th · ¸¸ ¹ α 2 · ¸¸ ¹ α Figure 2 : IV curve comparison of BSIM3 Vs Alpha Power model 5. IFFERENTIAL VCO BEHAVIOURAL MODEL The VCO is implemented using a 4-stage differential amplifier having a symmetric load [14]. The block diagram of the VCO along with the differential amplifier is shown in figure 4. Each stage of the differential amplifier consists of a diode-connected PMOS device in shunt with an equally sized PMOS device. The VCO control signal Vcn controls the current source associated with the differential delay element, while the Vcp controls the resistance of the symmentric load. At each stage, the Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE delay element output swings between Vdd and Vdd-Vcp. The delay of each stage varies with the load, the load in turn is controlled by the Vcp and the constant current source controlled by Vcn. by adjusting vcn (from figure 4b) so that the voltage at the output of the half buffer replica (vcp). Appropriate start up / initialization circuits are designed into the bias generator. Vcn/Vcp + - + + - Alpha Power Model + SPICE Figure 4a: VCO block Symmetric Load Vcp Fig. 5 VCO transient simulation Parameters Vth = 0.4013 α = 1.398 OV+ O+ Vth = 0.4275 V− α = 1.0417 Vcn Vth =0.3828 α = 1.1520 BSIM3 Alpha Power Model Model Frequency 1.948 GHZ 1.908 GHZ Maximum voltage 1.18 v 1.18 v Minimum voltage 0.29 v 0.31 v Voltage swing 0.89 v 0.87 v Table 1: VCO output: BSIM3 Vs Alpha power law comparison All transistors inside the bias generator are modeled by alpha-power law. Fig.6 shows the VCO characteristics simulated in Spectre-S. Figure 4b: Alpha Power Law model view 1.20 SPICE at N_1.2_25 fref 1.00 Frequency in GHz Each MOS transistor inside the differential delay stage is replaced with a alpha power law model. The performance of the VCO using alpha power model is compared against that of the BSIM3 based model in figure 5 at nominal process, 1.2V VDD at 25°C. Table 1 compares the VCO output characteristics using BSIM3 and the alpha power law models. The error variance of the VCO frequency in the alpha power model is found to be less than 2% of the BSIM based model. All the other characteristics like voltage swing, maximum and minimum voltage do not vary from the SPICE simulation. This shows the effectiveness of this model. Further, the simulation time reduces by a factor of 7 for a 25ns transient simulaton without loss of accuracy. In the self-bias architecture, bias generator generates both controls : Vcn that controls the constant current source, and Vcp that controls the symmetric load of the VCO. The Bias generator consists of an opamp and the vco half-buffer replica in feedback [14]. The function of the bias generator is to provide the constant bias current 1.40 Alpha at N_1.2_25 SPICE at W_1.08_125 0.80 Alpha at W_1.08_125 0.60 SPICE at S_1.32_-40 0.40 Alpha at S_1.32_-40 0.20 0.00 0.33 0.53 volts 0.73 Figure 6: VCO characteristics : SPICE Vs Alpha Power Law The %error between the alpha power law based and SPICE is found to be 3-4% at nominal process and 10- Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE 12% error at weak process, 8% at strong process. Layout parasitic have been back annotated into the PLL circuit at appropriate nodes. 6. Profile of the PLL phase step response is then monitored and the loop bandwidth and the damping factor calculated. Figure 8 shows the phase step response of the PLL using these behavioural models and its comparision against the BSIM model at 900MHz for a 1 µs transient simulation. Both the step responses are overlayed on top of each other for visual comparison. Loop bandwidth and the damping factor for the alpha power model are 4.8 MHz and 0.85 respectively. Corresponding BSIM3 SPICE simulation for the same conditions is 4.5 MHz and 0.97 respectively. The complete comparison for three different process, voltage and temperature (PTV) conditons is shown in table 2. CLOSED LOOP SELF-BIAS PLL SIMULATION A closed loop SPICE simulation was performed using the alpha power law models as shown in figure 7. PLL performance metrics compared are • Internal control node voltage (Vchpm, Vcp and Vcn) • Loop bandwidth • Damping factor • Cycle to cycle jitter • Simulation run time Simulation run time is bench marked using sunultrasparc10 333 MHz with 1GB main memory and 2.7GB virtual memory. Charge pumps, bias generators and VCO are modeled using alpha-power law model which is represented as dotted lines in figure 7. Digital components like PFD, Differential to single ended converter and counters are modelled at a functional level. Charge Pump1 φe Alpha power law model Ich1 C2 BSIM3 SPICE simulation C1 PFD fvco UP Bias Gen Charge Pump2 Vchpm DN Counter Alpha Power Model Vcp VCO f0 Vcn Diff 2 single converter Functional Model Figure 7: Self-Bias PLL architecture implemented using accurate behavioral model In the closed loop simulation, loop bandwidth, damping factor and the cycle-to-cycle jitter metrics were measured. In order to measure these metrics, first the PLL is allowed to lock into a particular frequency. Phase step is then applied at the reference input by changing the phase by 45 degrees. time φe Phase difference between reference clock and VCO generated clock at Phase Frequency Detector Input. Based on the simulation results, we conclude that the alpha-power law based behavioral models not only evaluate the PLL performance metrics with in 10% of BSIM3 SPICE but also reduce the simulation time by more than 75 times from SPICE run times. This alphapower behavioral model also evaluates the cycle-to-cycle jitter which none of the prior behavioral models addressed. Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE Parameter Nom, 1.08v, 40C Spice Strong, 1.08v, 125C Nom, 1.2V, 25C 0.543 α 0.51 Spice 0.462 α 0.475 Spice VCHPM (v) 0.582 α 0.59 VCN (v) 0.417 0.431 0.292 0.32 0.399 0.42 VCP (v) 0.461 0.475 0.542 0.51 0.582 0.59 BW (Mhz) 4.5 4.8 4.7 4.2 4.8 5.0 Damp. Factor 0.97 0.85 0.93 1.02 1.05 0.90 C-C Jitter (ps) Run time (sec) 6.34 6.03 4.01 6.34 6.02 5.13 97135 1172 98214 1182 97097 1139 Table 3: SPICE Vs Alpha power model at 900 Mhz 7. CONCLUSION The benefit of using the behavioral models in PLL design methodology is that it not only helps in reducing simulation run times but also allows the designers to explore the process, voltage and temperature space quickly. Analog PLL components such as VCO, charge pumps and bias generator that need to be modeled accurately are then constructed using alpha-power law behavioral models. Functional models are used to model the digital PLL components such as counters and Phase Frequency Detector (PFD). This mix of behavioral models is found to produce results that vary less than 10% from BSIM3 SPICE simulation and the simulation run-time is reduced more than 75 times. Alpha-power law model allows the designers to thoroughly explore process, voltage and temperature space through reduced simulation run times. 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Maneatis, "Low Jitter Process Independent DLL and PLL based on Self biased techniques", IEEE transactions of Soild state circuits, vol 31, no 11, pp 1723 – 1732, November 1996. [3] Walter Thain, Alvin Connelly, “ An Improved VCO macro model”, Circuits and Systems, pg 8-16, June 1992. [4] Alper Demir, et.al, “ Behavioral simulation techniques for Phase/Delay-locked systems”, Proceedings of IEEE Custom International circuit conference, San Diego, CA, USA, May 1994, pg 453-456. Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE