Design and Implementation of Monolithic Radio Transceivers Using Mentor Graphics Tools

Design and Implementation of Monolithic Radio Transceivers Using Mentor Graphics Tools Muhammad EL-SABA, ASU, isitech@lycos.com Abstract: In this paper we discuss the difficulties of design of analog/mixed systems, with emphasis on RF transceivers. We focus on the pertinent problems of system design, simulation, integration, test and verification. As a case study, we introduce the end-to-end design and verification methodology of a lowpower high-sensitivity mobile radio transceiver, operating at 1GHz using 0.35um CMOS technology. The end-to-end design includes: system design and analysis, architecture, pre-layout simulation, place and route, parasitic extraction, post-layout simulation and verification. We demonstrate how we could integrate system design tools, Mentor's ADMS simulation environment, with Mentor's physical implementation and verification tools, in a seamless way. So, we demonstrate the step-by-step design methodology for AMS systems in general, and RF transceivers in particular, by Mentor Graphics tools that span behavioral simulation, synthesis, layout, testing and constraint-driven optimization. I- Introduction Today's communications products require moving from concept to final product quickly. Current RF communication systems-on-chip include a wide range of devices operating at different frequency bands with different modulation and encoding techniques. On the other hand, the push for smaller handset size, longer battery life and more functionality continues to drive higher chipset integration. So, the commercial wireless industry has driven the need for automated RF-transceiver design, verification and testing methodology. The goal of the present work is to demonstrate circuit and system-level analysis of narrowband silicon radio transceivers The narrowband radio transceivers are usually used in mobile communication networks which employ a large number of channels stuffed in a small bandwidth. For instance, the AMPS standard system, allocates about 416 30-kHz forward, or downlink (base station to mobile phone), communication channels within a 12.5-MHz bandwidth assigned to a cellular service provider. As a case study, we demonstrate the design of narrow-band FSK/GMSK transceivers operating at 1 GHz. This article demonstrates many of the realworld impairments that can affect the narrowband transceiver system design. Simple tools like spreadsheets do not consider these impairments and provide inaccurate results during the initial phase of the design. By carefully implementing these effects via design simulation tools, accurate results can be achieved in the initial phase of the design to minimize manufacturing risk. In our work, we follow the Mentor Graphics standard AMS-IC design flow, which is adapted for our case study. The industrystandard IC design flow consists of 4 main phases [1]. In the algorithm design phase, we conceive the chip and generate specifications to system designers. Then the System/architecture designers begin to add structure to this simulation, partitioning the design into functional units. Hardware (prelayout) designers map the simulation to code (VHDL or netlist) and verify that the code matches the specified functionality. Finally Physical (layout) designers take standard-cell netlists synthesized from the code and use place-and-route tools to generate layout mask patterns for fabrication while verifying all design constraints. Fig. 1. The AMS IC- design flow. The paper is organized as follows; Section II depicts the system algorithm design. Section III recapitulates the system specifications. In section IV we demonstrate the transceiver architecture and operation. Then, we present the system analysis and design methodology in section V. In section VI we present the design issues of each building block. In sections VII, VIII we demonstrate the pre-layout simulation results and the layout of the transceiver frontend. In section IX, X we present the postlayout verification and testing procedures. Finally we present our conclusions in section XI. II – Algorithm Design The signal received by antenna should be transferred to the final form (voice or data) with high reliability (high signal to noise ratio or low bit-error rate) in the presence of noise and interfering signals. The receiver should have a wide dynamic range of inputs ranging from a few micro volts to several mill volts. The transceiver should also consume as little power as possible. S=-174dBm/Hz+10logBW+NF+SNRmin (dB) So, if we’d like to design a narrowband transceiver with BW=25 kHz and we’d like to achieve –107dBm (1uV) sensitivity at SNR=12 dB (BER=10-3), then we’d design the receiver such that its NF doesn’t exceed 11 dB. III. Developing System Specifications After defining the system global function and algorithm, we have to define its technical specifications. The radio transceiver specifications usually define the transceiver signal levels by the aid of a floating point analysis. The floating point (FP) model, is used to prove the feasibility of the system and serves as a reference for design specifications. Figure 4 depicts the FP model of a radio transceiver. Fig. 2. Radio receiver functional diagram. In the transmitter direction, the baseband signal should be transmitted with appropriate power and frequency, as efficiently as possible. There exist several metrics which can be used to evaluate the success of the data transmission. The most common metric, in the case of digital signals, is the received Bit Error Rate (BER). Other valuable performance indicators include the received Signal-to-Noise Ratio (SNR), eye Patterns and Phase Scatter Plots, to name a few. We dully note that the SNR of a receiver is related to the BER and the so-called noise figure (NF) of a receiver is defined as follows: NF = 10 log ( SNRin / SNRout ) Fig. 3. Floating point model of a radio transceiver. For our case study, the main specifications are as follows. Receive Frequency Bands: Base Station 880 – 892.5 MHz Mobile Unit 901 – 913.5 MHz Modulation: FM/FSK/GMSK SNR/BER: > 12dB (BER= 10-3) Power consumption < 300 mW Sensitivity < -107dBm (RF) Channel Spacing: 25 kHz. The minimum detectable (discernable) signal is affected by the receiver NF and bandwidth (BW) and is given by: IV - System Design MDS =-174dBm/Hz +10 log BW+NF(dB) At first, we have to choose a transceiver topology. There exist two transceiver topologies, according to the mixing procedure: The receiver sensitivity (S) is defined as the minimum input signal that could be reproduced at the receiver output with minimum acceptable SNR: S = Ps,min =MDS +SNRmin (dB) So, the receiver sensitivity is affected by its NF and may be expressed as follows: Direct Conversion (Zero-IF) transceiver, in which the local oscillator frequency (LO) is equal to the RF frequency Heterodyne transceivers, in which the local oscillator frequency (LO) is not equal to the RF frequency Fig. 4. Super-heterodyne receiver architecture. The zero-IF topology has two major drawbacks that makes it hard to achieve an acceptable performance. The first source of performance degradation is inherent to any analog integrated multi-path topology. Excellent matching between the different down-conversion paths is required but limited in analog implementations. The effects of mismatch, i.e., phase and amplitude errors, degrade the signal quality because they result in a reduced mirror signal suppression. In addition, its baseband configuration of the zero-IF topology is highly sensitive to parasitic baseband signals like DC offset voltages and self-mixing products caused by cross-talk between the RF and the LO signals. From the analog/digital perspective, there exist different types of RF transceivers, namely: RF-ADC transceiver (all digital) IF-ADC transceiver Baseband-ADC transceiver An all digital receiver demands RF-ADC, which is not practical with current technology. So, our choice is ported to the advantages in a transceiver with super-heterodyne analog front-end that delivers control into the hands of the user. In analog, infinite tuning is available in order to establish maximum stereo separation or to detune slightly in order to minimize on-frequency noise. signal. For analog signals, it is often desirable to digitally encode the signal prior to transmission by undergoing a quantization process (ADC). While some information is lost in this process, the resulting digital signal is often far less susceptible to the effects of noise in the transmission channel. The role of system analysis is to-trade off between different design issues such that the whole transceiver performance is optimized. In the system analysis we tried many system design tools such as: • SystemC, from OSCI [2] • MATLAB (Simulink), from MathWorks [3], • SystemView, from ELANIX [4], • CommLib from Mentor Graphics [5] SystemC, is an open community C++ modeling platform for system-level design and hardware/software co-design. For the time being, SystemC doesn’t support AMS. Communications libraries, like CommLib from Mentor Graphics [5], contain a set of modules to aid rapid design of communication Systems. These Math-based tools make use of cascaded blocks. Figure 5 depicts the block diagram and the system analysis of a frequency synthesizer (FS), using CommLib. The FS is used in RF transceivers to generate stable local oscillator (LO) signals at precise frequencies, with minimum phase noise, and minimum switching time. As shown, the presented FS is composed of a phase-locked-loop (PLL) with a programmable frequency divider. The PLL is composed of a voltage controlled oscillator (VCO), a frequency divider, and phasefrequency detector (PFD), a charge pump (CP) and a low pass filter (LPF). The designers of PLL-based synthesizers usually face tradeoffs related to the resolution, convergence speed, power consumption and phase noise of the synthesizer. The basic factor that limits the performance of the synthesizer is the low sampling rate of the phase difference. The sampling rate is dependent upon the frequency step of the synthesizer. V - System Analysis The transceiver elements can be subdivided into sub-systems, as shown in figure 3. These include a data source (analog or digital), an optional data encoder, a modulator, a demodulator, and optional data decoder. The data source generates the information signal to be sent to a particular receiver. This signal can be either an analog signal such as speech, or a digital signal such as a binary data sequence. This signal is typically a baseband It should be noted that the spurious noise is another example of the real-world impairment often seen in RF transceivers. Spurious response is usually generated by nonlinear amplifiers such as mixers, as well as spectrally impure local oscillators. To analyze spurious signals, the designer needs adequate selectivity ahead of the mixer stage and good linearity in the LNA stage to obtain a wide, spurious-free dynamic range (SFDR). Traces of spurious frequencies, and power levels for all nodes of the design can be better determined using circuit simulation tools, because it depends on the transceiver architecture. modulation terms will decrease the practical sensitivity of the receiver. Increasing the sensitivity of the receiver will NOT solve the problem, but increasing the linearity of the receiver solves it [6]. We duly note that the linearity of the receiver is closely related to the third-order input intercept point (IIP3). It is NOT possible to maximize IIP3 and sensitivity and minimize current consumption of a receiver, at the same time. The best trade-off is found, through optimization, for minimum power consumption with maximum reception sensitivity. Figure 6 depicts the global system analysis results. Fig. 5-a. Block diagram of the FS Fig. 6. The global system analysis results. VII- Transceiver Architecture Fig. 5-b. System analysis results of the FS. In this section we demonstrate the architecture of the transceiver front-end building blocks. The band selection is performed using an LNA pre-select filter, to reduce image rejection (IR) requirements. The channel selection is to be performed using frequency synthesizer. A. LNA Architecture Fig. 5-c. The FS settling step response. The global system analysis we made, resulted in the following conclusions: the more RF gain, the more relaxed noise specifications. So, the gain of the LNA reduces noise requirements on mixers and baseband variable gain amplifiers. In the presence of a pair of interference sources, unwanted in-band inter- The LNA is implemented as a cascode amplifier with inductive-degeneration, as shown in figure 7. The heart of the LNA is a source-degenerated MOSFET (M1), in cascode configuration with M2 to increases the LNA isolation. The LNA is designed for achieving NF <1.5 dB and power gain >10 dB at fo = 870-990 MHz. In order to match the LNA with the previous stage, we provide a real input impedance equal to the source resistance (or antenna radiation resistance), to cancel the reactive component at input circuit. A number of solutions exist to provide input matching: Resistive termination, 1/gm degeneration, shunt-series feedback and inductive degeneration. Schemes involving resistors add thermal noise which degrades noise figure and increases power dissipation. Matched resistors can be made within 1% but process variations in poly, for example, can be as high as 30%. The 1/gm biases suffer from poor noise figure due to gate noise current at high frequencies. The inductive degeneration is more amenable approach. Adding an inductance to the source of the MOS contributes a real term in the input impedance without the poor noise performance of a resistor. The reactive component of the input impedance can then be tuned using a second inductor on the gate (Lg). Fig. 8. The mixer architecture. Fig. 7. Narrow-band LNA architecture.. B. Mixer Architecture The main purpose of the mixer is to translate the input RF signal to IF signal without corrupting it by noise or distortion. The important criteria that should be considered when designing a mixer are: linearity, noise, power consumption, and conversion gain. The mixer circuit shown in Fig. 8 is composed of a double-balanced Gilbert cell, with differential LO input and differential IF output. The double balanced or Gilbert cell mixer is most desirable for high port-to-port isolation and spurious output rejection applications. The mixer circuit is designed to provide high gain (about 10dB) and very low noise figure (about 10 dB) in a wide frequency range (30MHz1GHz). To eliminate the need to a balun transformer in its connection with a singleended LNA, the mixer is driven with one side AC-grounded. It exhibits similar performance to its differential counterpart except that it has lower dynamic range. In order to operate the mixer at low voltage, the biasing circuits and current mirrors are deliberately designed for minimum headroom. C. Frequency Synthesizer Architecture As shown in figure 9, the FS circuit is based on the charge pump PLL architecture [6]. In order to cope with switching phase noise problems, we employ a programmable dual modulus divider with input prescaler and a low phasenoise LC-tuned VCO (shown in Fig. 10). Fig. 9. Block diagram of the FS . Fig. 10. Block diagram of the VCO. D- IF/limiter Amplifier An IF/limiting amplifier (IFLA) is usually implemented after the IF filter, in FSK/FM receivers, where no information is present in the signal amplitude. The IFLA can provide a rail-to-rail output voltage, which is suitable for the demodulation stage or to drive logic gates in the subsequent digital blocks. The block diagram of the IFLA amplifier with feedback network is shown in Fig. 11. The IFLA consists of 8 amplification cascaded stages with a common-mode feedback network for gain control and DC-offset cancellation. The DC-offset is one of the main problems in limiting amplifiers that degrades the operation of, not only the IFLA but also, the subsequent stages [7]. This DC-offset voltage may be cancelled by large coupling capacitors, before the limiters, which takes large silicon area, especially for low-IF transceivers. However, here the DC offset is cancelled by proper adjustment of the feedback network. The 6 intermediate stages are exactly identical but the first and last stages differ in the transistors sizes and active load. The limiting function of the IFLA is performed by a CMOS inverter (d). The intermediate stage (a). The IFA/Limiter building blocks (e). The final amplifying stage Fig. 11. The IFA/Limiter building blocks. (b). The input mixing stage VIII- Pre-layout Simulation The pre-layout simulation is carried out using ADMS simulation environment, from Mentor Graphics [5]. Fig. 12-a, depicts the LNA gain, and noise figure (NF). Fig. 12-b demonstrates the VCO output (LO+, LO-). (c). The limiting stage Table1 indicates the time it takes for transient simulation to determine the FS settling time, using different simulators It should be mentioned, that the CommLib is written in behavioral language (VHDL-AMS), and hence runs faster, but with less accuracy [8]. In the above mentioned results, we made use of behavioral simulation in the ADMS environment, only for the digital blocks. decrease interference and increase the noise immunity. PSF/LNA Mixer Fig. 12-a. Gain and noise figure of the LNA. IF/Limiter/Demodulator FS / VCO Fig. 13. Layout of the transceiver receiving path. Fig. 12-b. The output voltage of the VCO. Table 1. FS settling time simulation results. Simulator ADMS ELDO ELDO RF ELDO RF ComLIB Condition MACH 1H 1.2 Time 10 us days 12 min 4 H 2.5 us 22 sec IX- Layout & Parasitic Extraction Figure 13 depicts the layout of the transceiver receiving path. The layout is performed using ICStation, from Mentor Graphics [5]. The layout of analog blocks is performed using the schematic-driven layout (SDL) tool. As for digital blocks, we made use of the layout automatic generation of standard cells. As shown in figure, the LNA inductors are implemented using bond wires and the coupling capacitors are integrated as differential components to decrease the mismatch between them. Also, all the CMOS transistors and integrated coupling capacitors are inter-digitized to reduce mismatch. Also, all building blocks are surrounded by ties to The step following the silicon layout is to apply the design rules checker (DRC) to make sure that there is no violations of the adopted technology layout-rules. After performing the DRC with no errors, the layout-versusschematic (LVS) is done. Finally, we made use of the ICextract tool to perform the parasitic extraction. This tool extracts the parasitic capacitances and resistances, which are added during the silicon layout procedure. X. Functional Verification Silicon (post-layout) verification involves checking whether the hardware design is correct, assuming it has been implemented correctly. The goal of this debugging process is to find any remaining design errors that might have slipped through the pre-silicon phase. Because of the lack of an adequate built-in-self-test (BIST) tools for AMS circuits in general and RF transceivers in particular [9], we adopt a specification-driven, with intrusive verification methodology [10]. So, the digital blocks of the transceiver are verified via standard digital methods, namely: the delaypower testing strategies [9]. The AMS blocks of the transceiver are verified with other strategies, very specific to the particular type of circuitry such as the power gain and noise figure. The post-layout simulation is performed using ADMS. We made transistorlevel simulation using ELDO-RF. Tables 2, 3 summarize the simulation results of the LNA and the mixer. level based on early verification and constraint propagation; bottom-up accurate extraction and verification; automatic and interactive synthesis of components with specification constraint-driven layout design tools; with support for automatic synthesis tools and consideration for testability at all stages of the design. Fig. 14. The limiting amplifier output. Table 2. LNA post-layout simulation results. Parameter Value Frequency range 870-990 MHz Gain 11 dB Input IP3 11 dBm NF 1.13 dB Bias 3.3V Input return loss (S11) -12 dB Output return loss (S22) -15 dB Table 3. The mixer simulation results. Mixer type Gain NF P1dB Single-ended 9.3 10.7 -12 Gilbert Cell dB dB dBm IIP3 -2.7 dBm XI. Conclusions In this paper we demonstrated the system-level design and circuit analysis of narrow-band radio transceivers. In our system analysis we made use of the behavioral models of Mentor Graphics’ CommLib. RF behavior models are commonly used in high-level system design in most system design software. The advantage is that behavioral models reduce system simulation time. The disadvantage is often a compromise in results accuracy. On the other hand, behavioral models that are extracted from circuit level components reduce simulation time and provide more accurate results. These models contain RF circuit impairment effects, S-parameters, power, and narrowband effects. The co-simulation using system tools in conjunction with the Mentor simulation environment ADMS highlights the use of transistor-level circuit descriptions within a system-level simulation. Detailed analysis of our case study shows how to obtain important transceiver parameters, such as gain, noise figure, third-order inter-modulation products, and IP3. In our analysis, we adopt a top-down constraint-driven design, with intrusive verification methodology. The key points of this methodology are: top-down hierarchical process starting from the system Fig. 15. Design-flow gaps. The advantage is that behavioral models reduce system simulation time. The disadvantage is often a compromise in results accuracy. On the other hand, behavioral models that are extracted from circuit level components reduce simulation time and provide more accurate results. These models contain RF circuit impairment effects, Sparameters, power, and narrowband effects. References: [1] William R. Davis, A Hierarchical, Automated Design Flow for Low-Power, High-Throughput Digital Signal Processing IC’s, PhD Thesis, UCB, 2002. [2] Open SystemC Inc., www.sytemc.org [3] Matlab, Mathworks, www.mathwork.com [4] SytemView, Elanix, www.elanix.com [5] Mentor Graphics Corp., www.mentor.com [6] L. Lin, Design Technology for High Performance Integrated Frequency Synthesizers for Multi-standard Wireless Applications, PhD thesis, UCB, 2000 [7] S. Martin an R. Olsson, “A 150-MHz low power CMOS IF-Baseband Strip for GSM”, IEEE Trans. SSC, Sept. 2000. [8] Marius Sida, Rami Aloha and Daniel Wallner, Bluetooth Transceiver Design and Simulation with VHDL-AMS, IEEE Circuits & Systems, Vol.19, No.2, March 2003. [9] R. Rajsuman, System-On-Chip Design an Test, Artech House, Boston, 2001. [10] H. Chang et al. “A Top-Down ConstraintDriven Design Methodology for Analog Integrated Circuits”, Kluwer Academic Publishers, 1997.