Academia.edu no longer supports Internet Explorer.
To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser.
2000
Abstract Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise.
2001 •
Abstract CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise.
2012 •
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.
2015 •
FPGA-Based Systems Increase Motor-Control Performance Powering ICs On and Off Design a PLL Loop Filter when Only the Zero Resistor and Capacitor Are Adjustable Quickly Implement JESD204B on a Xilinx FPGA Power Management for Integrated RF ICs Design Reliable Digital Interfaces for Successive-Approximation ADCs 2 3 11 15 21 25 31 A forum for the exchange of circuits, systems, and software for real-world signal processing • Volume 49, Number 1, 2015 Analog Dialogue
2008 •
2011 •
There is a strong need for stable frequency references with large tuning ranges in today‟s communication systems. While the crystal oscillators assure good frequency stability, it is not possible to achieve a large frequency range by tuning the passive components attached to them. Frequency synthesizers are usually used for this purpose because of their ability to produce a variety of output frequencies. The Phase Locked Loop (PLL) based frequency synthesizer is the most preferred of all types of synthesizers available because of its additional features like programmability, low noise and low cost as well as high accuracy and stability. The main idea of this PLL-based synthesizer is to phase-lock its output signal with an input reference signal and to produce a synchronous output. It does this by generating an error signal to correct the oscillator frequency. This functionality is achieved by integrating a phase detector, charge pump, loop filter and voltage controlled oscillator bl...
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003
A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz2003 •
2014 •
Technology scaling and unprecedented growth in demand for ubiquitous, fast, robust computing have been the driving forces leading the innovations in high-speed interfaces. With the rise of heavy duty data centers to handheld mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high and has led the roadmap of the semiconductor industry, making it one of the fastest growing yet fiercely competitive industries. With the growing needs for ultra-low power yet multi-Gbps signaling in both wired as well as wireline applications, integrated systems on chip (SoCs) have become mainstream critical components in modern computing systems. The ability to process and access ‘big-data’ is the fundamental demand in modern society where every second saved in prompt communication as well as computation of information is critical. In order to meet these needs of fast, robust signaling over the same old “lossy” channels, the clock-frequencies nee...
2003 •
2006 Proceedings of the 32nd European Solid-State Circuits Conference
A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication2006 •
IFIP Advances in Information and Communication Technology
Analysis and Design of Charge Pumps for Telecommunication Applications2010 •
2011 •
Mc Graw Hill Education
Design of Analog CMOS Integrated Circuits Second Edition2017 •
IEEE Journal of Solid-State Circuits
A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links2000 •
Journal of Electrical and Computer Engineering
Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration2013 •
Photonics Packaging, Integration, and Interconnects VIII
<title>Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect</title>2008 •
2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)
An accurate analytical spur model for an integer-N phase-locked loop2012 •
2006 •
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers
A multiphase PLL for 10 Gb/s links in SOI CMOS technology2004 •
2009 IEEE Custom Integrated Circuits Conference
Discrete-time, cyclostationary phase-locked loop model for jitter analysis2009 •
2005 •
Proceedings of International Conference on Computer Aided Design
A video driver system designed using a top-down, constraint-driven methodology1996 •
2018 •
2014 •
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
Use of sensitivities and generalized substrate models in mixed-signal IC design1996 •
Solid-State Circuits IEEE International Conference
A PLL clock generator with 5 to 110 MHz lock range for microprocessors1992 •
IEEE Journal of Solid-State Circuits
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications2000 •