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2004
Abstract Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed.
2005 •
Abstract This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling ΔΣ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the ΔΣ modulator is studied.
2003 •
Abstract This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling DS modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the DS modulator is studied.
2001 •
Abstract CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise.
2002 •
Abstract Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-locked-loops are widely used as clock generators of microprocessors.
2000 •
Abstract Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise.
IEEE Journal of Solid-State Circuits
A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications2000 •
Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applications have almost exclusively employed the use of a charge-pump phase-locked loop (PLL), which acts as a local oscillator (LO) for both transmitter and receiver. Unfortunately, the circuits and techniques required are extremely analog intensive and utilize a process technology which is incompatible with a digital baseband. The author’s research related to low-power and low-cost radio solutions has led to a novel all-digital synthesizer architecture that exploits strong advantages of a deep-submicron digital CMOS process technology as well as advances in digital very large scale of integration (VLSI) field. Its underlying theme is to maximize digitally-intensive implementation by operating in a synchronous phase domain. Chief benefit obtained with this architecture is to allow to integrate the RF front-end with the digital back-end onto a single silicon die. The presented frequency synthesizer naturally combines the transmitter modulation capability implemented in an all-digital manner. The pulse-shaping transmit filter and a class-E power amplifier are included to demonstrate the use of the proposed synthesizer in a targeted RF application. The ideas developed in this research project have been implemented in a Texas Instruments’ deep-submicron CMOS process and demonstrated in a working silicon of BLUETOOTH transmitter for short-range communications.
2006 Proceedings of the 32nd European Solid-State Circuits Conference
A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication2006 •
Proceedings of the IEEE
Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation2000 •
Circuits and Systems (MWSCAS), …
Design of low-voltage wide tuning range CMOS multipass voltage-controlled ring oscillatorIEEE Journal of Solid-State Circuits
A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links2000 •
2014 •
IEEE Journal of Solid-State Circuits
40-43-gb/s oc-768 16:1 MUX/CMU chipset with SFI-5 compliance2003 •
IEEE Journal of Solid-state Circuits
An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel1994 •
IEEE Journal of Solid-State Circuits
A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology2003 •
IEEE Journal of Solid-State Circuits
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications2000 •
2008 •
Proceedings of the IEEE
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits2000 •
2008 •
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
Use of sensitivities and generalized substrate models in mixed-signal IC design1996 •
2007 •
2007 •
2008 •
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003
A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz2003 •
IEEE Journal of Solid-state Circuits
A single-chip 9-32 mb/s read/write channel for disk-drive applications1995 •
IEEE Transactions on Electromagnetic Compatibility
Electromagnetic Susceptibility Analysis on a Digital Pulse Width Modulator for SMPSs2000 •
IEEE International Conference on Robotics, Intelligent Systems and Signal Processing, 2003. Proceedings. 2003
A low power frequency synthesizer with an integrated negative transconductance LC-tuned VCO2003 •
IEEE Journal of Solid-State Circuits
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors2000 •
Solid-State Circuits, …
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture1996 •
IEEE Journal of Solid-State Circuits
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS2000 •
IEEE Journal of Solid-State Circuits
Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC2000 •
2002 •
VLSI Circuits, 1995. …
A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture1995 •
Integration
A PLL-based synthesizer for tunable digital clock generation in a continuous-time S ? A/D converter2009 •
IEEE Journal of Solid-state Circuits
Circuit techniques in a 266MHz MMX-enabled processor1997 •