ARTICLE IN PRESS INTEGRATION, the VLSI journal 42 (2009) 24–33 Contents lists available at ScienceDirect INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi A PLL-based synthesizer for tunable digital clock generation in a continuous-time SD A/D converter Jokin Segundo , Luis Quintanilla, Jesús Arias, Lourdes Enrı́quez, Jesús M. Hernández, José Vicente Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain a r t i c l e in f o a b s t r a c t Keywords: Phase locked loop Clock generation Ring oscillator Phase noise Continuous-time SD converter In this paper, the design and implementation of a tunable clock synthesizer for driving two continuoustime SD ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a 0:35 mm CMOS technology. The frequency of the clock ranges from 12 to 256 MHz with a minimum tuning step of 10 kHz. The PLL phase noise is kept below 80 dBc=Hz at 1 MHz offset for the entire output range, while drawing 2.2–5.6 mA from a 3.3 V supply voltage. & 2008 Elsevier B.V. All rights reserved. 1. Introduction Nowadays, there is a ever growing trend to integrate a communication system front-end as far as possible in a standalone silicon chip. This trend forces the analog and digital sections of the transceiver to share the same substrate, demanding robust mixed-signal designs and good isolation between the high frequency/RF analog section and the IF/baseband digital signal processing [1,2]. Nevertheless, the continuous decrease in the feature size in CMOS technologies, together with the faster clocking rates, allows higher frequencies to be directly processed in the digital domain, pushing the digital circuit blocks closer to the physical medium (wires or antennas). This approach benefits the repeatability of digital filters and mixers, and the lower supply voltages and low power consumption of the digital circuitry. Applications range from high-speed baseband processing (for instance, ADSL or Gigabit Ethernet) to radio signals (such as AM or FM broadcasts). The main constraints of the receiver are now put into the analog to digital converter. The desired amplitude ranges usually vary over several dBs (e.g., due to fading in analog radio broadcasting), and a minimum signal-to-noise ratio (SNR) has to be kept in order to demodulate without too many errors. As a competitive alternative to Nyquist-rate (flash, pipeline, etc.) converters, sigma–delta ðSDÞ ADCs achieve very good resolution values without the need of extremely good circuit building blocks, trading sampling frequency for accuracy. These converters are clocked at a rate higher than the Nyquist frequency, and use noise  Corresponding author. Tel.: +34 983 423000x5656; fax: +34 983 423675. E-mail address: jokseg@tel.uva.es (J. Segundo). 0167-9260/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2008.07.002 and mismatch shaping techniques, which require extensive digital signal processing, to obtain SNRs even higher than 60 dB (10 effective bits) [3]. SD ADCs can be designed to be band pass, instead of low pass like it is mandatory in other kind of converters, allowing the direct digitization of the radio channel of choice. In this case, tuning in a band pass sigma–delta converter can be done by changing the clock frequency, and PLL-based synthesizers are a suitable choice for the generation of accurate frequencies for both demodulation and clocking. Even though the analog section of these SD converters is implemented following a discrete-time approach and based on switched capacitor or switched current circuits, the higher speed and inherent antialiasing of the continuous-time SD ADCs has made them an interesting design choice for the aforementioned applications (see, for instance, [4]). Nevertheless, continuous-time circuits are sensitive to clock jitter (see, for instance, [5]), demanding a limited clock phase noise in order to avoid the increase in noise floor, as it reduces the achievable dynamic range and resolution of the converter. In this article, the design and implementation in a 0:35 mm CMOS technology of a PLL-based tunable synthesizer for clocking two continuous-time SD ADCs (low pass and band pass) is proposed. First, the overall system description is presented by considering the complete chip architecture and the impact on CT sigma–delta modulators of the clock phase noise. The tuning capability of the frequency synthesizer has been emphasized. Next, the design of the phase locked loop is discussed. In particular, system level simulations were used to establish the PLL phase noise requirements. In Section 4 the PLL building blocks are described, and in Section 5 transistor level simulations are accomplished. In Section 6 experimental results measured from a manufactured prototype are shown and discussed. Finally, conclusions are summarized. ARTICLE IN PRESS J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 2. Overall system description band pass converter, allowing the direct digitization of the narrow channel of interest without the need of analog downconversion. This way, all the signal processing can be done in the digital domain. This approach asks for a wide tuning range with a small frequency step, while maintaining a clock phase noise appropriate for the application. 2.1. Complete chip architecture Our designed test chip contains two continuous-time SD modulators, together with a shared decimator, and the clock generation circuitry, based on a phase locked loop. A simplified block diagram is depicted in Fig. 1. Sigma–delta analog to digital converters are mixed-signal circuits, which contain both analog and digital circuitrics. The main building blocks of a SD ADC are the modulator and the decimation filter [3]. The modulator generates a high sampling rate digital sequence with a low number of bits from the analog input samples. This high rate sequence is later filtered and decimated in order to obtain the data with a lower sampling rate and a much better dynamic range, giving rise to more bits of resolution. One of the converters is a current mode, low-pass ADC (LP SD) with a bandwith of 1 MHz, intended to work with ADSL signals [6], and the second one is a tunable band pass ADC (BP SD) intended to digitize radio signals lying in the short wave (HF) band [7]. While the first modulator operates with a fixed clock frequency of 256 MHz, the second one has to be tunable in order to cover frequencies ranging from 3 to 30 MHz. As the channel to be selected is always located at f s =4 due to the chosen architecture, this second converter requires a 12 –120 MHz tunable clock. The modulators usually found in the literature are clocked either by an external low-jitter clock generator [8] or an on-chip PLL that multiplies the frequency of an external reference oscillator [9,10]. In both cases, the clock frequency of the modulator is fixed, and the PLL merely works as a frequency multiplier, rather than as a frequency synthesizer. Moreover, the voltage controlled oscillators (VCOs) employed are habitually of an LC-type, achieving a good phase noise figure at the expense of occupying a large amount of area, and having a very narrow tuning range. Some of the implementations achieve coarse tuning by means of an array of capacitors to overcome the process variations, but then its operation is restricted to a small frequency range near the VCO center frequency [11]. However, in our chip the goal is to use the tuning capability of the frequency synthesizer to modify the center frequency of the BP Σ∆ CLK Vin 2.2. Impact on CT SD modulators of clock phase noise No clocking scheme can provide a perfectly accurate frequency, and drifts occur due to various phenomena. While long-term frequency drifts are mainly caused by the operation temperature of the oscillator and aging of the components, short-term variations are mainly originated by the electronic noise and couplings in the oscillator circuit [12,13]. This fluctuations in the instantaneous frequency of the synthesized frequency are called phase noise, and limit the overall performance of the system, for example in RF transceivers [14] or continuous-time SD modulators similar to the two included in our chip. It is well known that clock jitter degrades the performance of continuous-time SD ADCs (see, for instance, [5]). This effect generates random fluctuations of clock edges. The time uncertainty occurring at both two edges in every period generates both white noise on the output spectrum (increasing the noise floor) and skirts on tones. In particular, for continuous-time SD modulators, a change in the DAC current pulse width causes a deviation from the accurate amount of charge that should be fed back into the integrators for ideal modulator operation, thus resulting in a jitter-induced input referred noise. Jitter and phase noise are closely related, and for a given phase noise LfDf g at frequency offset Df from the carrier ðf 0 Þ, the cycleto-cycle jitter scc, defined as the rms value of the length difference between pulses, can be calculated [15] as scc ¼ Df 3=2 f0  10ðLfDf g=20Þ From config register Digital Filter 0 0 MUX 1 1 LP Σ∆ CLK 1/4 Ref. CLK PLL PFDout VCOin R C1 (1) According to this expression the frequency dependence in Eq. (1) makes the phase noise requirements to increase with decreasing frequencies, given a fixed frequency offset and percentage of period requirement for the jitter. MUX Iin 25 C2 Fig. 1. Block diagram of the complete designed test chip. CLK Digital output ARTICLE IN PRESS 26 J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 3. Phase locked loop design The block diagram of the proposed PLL is shown in Fig. 2 and the design discussion is detailed next. 3.1. Frequency planning Although short wave radio receivers in the HF band have very narrow channels, a very low reference frequency is not practical, because the corresponding divider factors would be too high. The minimum PLL tuning step has been selected to be 10 kHz, which corresponds to 2:5 kHz tuning steps in the radio frequencies. Finer tuning should be done in the digital domain by means of digital mixers and filtering. The frequency multiplication in the loop requires the presence of a divider in the feedback path with a programmable division factor ranging from 1200 (for the 12 MHz clock) to 25600 (for the 256 MHz clock required in the low-pass ADC). The highest factor imposes the length of the counter word to be 15 bit. This choice of dividers forces the VCO tuning range to cover the entire 12–256 MHz range, which spans more than four octaves, with the required phase noise. Since this is a hard specification to meet, it was chosen to separate the frequency division in two steps using a prescaler with a programmable factor allowing us to relax the specs for the VCO. In consequence, the VCO tuning range was reduced to 96–256 MHz, one and a half octaves, easing the selection of values for the tuning elements. been used. A Runge–Kutta integration method was employed to solve the differential equations that describe the circuit. In order to focus our attention on the effect of clock jitter, simulations only consider quantization noise and clock jitter, which was modeled by modifying the clock period randomly. The input signal was synchronized with the clock, and the included jitter mainly modifies the DAC’s pulse width. In Fig. 3 two simulated spectra are shown together for comparison. An ideal band pass modulator has been considered in the first simulation, where a deep notch can be seen at f s =4. On the contrary, when clock jitter is added to the simulation (1% of the 120-MHz clock frequency), the notch is filled in, increasing the noise floor and making the converter resolution to decrease. In addition to clock jitter, the other noise sources mentioned above must be taken into account, in particular, thermal noise. We have proved previously [7] that thermal noise is the most limiting factor of the modulator performance, thus masking the effect of any other source of noise, while they are kept below the thermal noise floor. The specified SNR value for both converters is at least 60 dB, in order to reach 10 effective bits of resolution. Simulations including all the noise sources detailed above provide a target phase noise spec of 80 dBc=Hz at 1 MHz offset for the clock generation circuitry. This nondemanding phase noise value is 0 -20 3.2. Phase noise requirements Since the phase noise requirement is probably the most significant PLL spec for our application, simulations must be carried out to determine the highest tolerable clock phase noise for the proper operation of the modulators driven by the PLLgenerated clock. In particular, the band pass modulator was considered due to its tunability requirement. Transistor-level simulations (Spice-like) are time consuming and they do not allow the simulation of noise for time-domain analysis. Therefore, a system level simulation program in C was developed in order to fill these needs including the effect a broad set of non-idealities specially thermal noise, 1=f noise and clock jitter [16]. To take into account the continuous-time behavior of the system, a time step much lower than the clock period has VCOin VCO 1/2 Amplitude (dB) -40 w. Jitter -60 -80 -100 Ideal -120 -140 15 20 25 30 1/2 1/2 MUX Sel Prescaler 1/2 From config. register CLK (to other chip blocks) PFD 1/N Loop divider 16 bits Ipump PFDout 40 45 Fig. 3. System level simulated output spectra for the band pass modulator showing the effect of jitter. An input tone with a frequency of 5 kHz away from the 30 MHz carrier has been applied. # FFT samples: 219 . A Hanning window was used. Ref. CLK Reference 1/M divider 12 bits 35 Frequency (MHz) 1/2 Fig. 2. Block diagram of the designed PLL. CLK_MON (clock measurement pin) ARTICLE IN PRESS J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 related to the narrow channel width required for our application, and its corresponding integrated in-band noise. 3.3. PLL design tradeoffs Jitter and phase noise are affected by the PLL dynamics. In locked state, the equivalent phase response of a PLL is that of a low-pass filter [17]: HðsÞ  Fo ðsÞ ðK=NÞFðsÞ ¼N s þ ðK=NÞFðsÞ Fr ðsÞ (2) where FðsÞ is the transfer function of the loop low-pass filter after the phase detector, K ¼ 2pK d K VCO ; K d the phase detector gain in V/Hz, K VCO the VCO gain in Hz/V, and N the feedback loop division factor. Therefore, two regions can be considered in the phase noise response [18]. The first one comprises the passband of the filter in Eq. (2), where the main contribution to phase noise comes from the filtered reference phase noise multiplied by N. The second region falls out the loop bandwidth, where the VCO is essentially in an open-loop configuration and its phase noise appears at the clock output. In our design, the loop bandwith was established from the phase noise specification required for our application, so as to minimize the contribution of the reference phase noise. Thus, the loop filter bandwidth was kept low (several kHz), forcing the corresponding settling time. As the converter tuning time is not a demanding spec in this application, the settling time can be relaxed. 4. Circuital building blocks The PLL building blocks shown in Fig. 2 are implemented in a 0:35 mm CMOS technology and described next. 4.1. Prescaler and frequency dividers The external oscillator used to generate the phase reference for the PLL has been implemented with a 20 MHz low phase noise quartz crystal. In order to achieve the desired minimum PLL tuning step of 10 kHz in the synthesized clock rate, the reference 27 must be divided by a factor of 2000. This is obtained by means of a 12 bit counter, depicted in Fig. 4, implemented with a chain of T-type flip-flops whose architecture consists of a master–slave Dtype flip-flop and a feedback multiplexer. The division factor is set by changing the values stored in the configuration shift register to allow flexibility in the measurements. Since the phase-frequency detector (PFD) is triggered by reference edges, not by its levels, the very low duty cycle reference signal can be directly used. The loop divider has a similar implementation, but it requires an additional 4 bit divider. It is based on a chain of 16 T-type flipflops with a synchronous load of the division factor. Every time the counter reaches zero, a short pulse appears at the output. On the other hand, the prescaler consists of a series of flip-flops, each halving its clock frequency, whose outputs are multiplexed, as seen in Fig. 2. Consequently, the resulting prescaler factors are powers of 2, selectable from 1 to 16, and later fed to the loop divider. 4.2. Voltage controlled oscillator The major choice taken in the VCO design was the selection of a differential cell for the oscillator core [15,19]. Even though singleended inverter cells achieve a lower phase noise for the same power consumption, and differential cells can have an increase in close-in phase noise due to the reciprocal mixing of the flicker noise of the tail transistor, these later ones are less sensitive to common-mode noise, such as power-supply noise or substratecoupled noise. These noise sources arise in mixed-signal circuits due to the switching in the digital sections of the circuit, and couple to the analog section, degrading its performance. Thus, common-mode noise must be properly rejected, leading to the choice of a differential topology for our design. The designed VCO topology is shown in Fig. 5. The ring oscillator consists of only three differential inverter cells in order to keep the power budget as low as possible, as no intermediate phase is necessary. The circuit schematics for one of these inverter cells is shown in Fig. 6, whose component sizes are listed in Table 1. The approach taken to achieve the frequency tuning was to employ PMOS loads in the triode region (M 3 and M 4 ), modifying their resistance, and thus, the RC delay of each cell. Good TC E T Q L /Q P T Q L /Q P T Q L /Q P T Q L /Q P CLK LOAD 4 bit divider P0 VDD P1 E P2 TC E 4 bit divider CLK LOAD P3 E TC Pn CLK LOAD OUT (CLK/M) TC 4 bit divider 4 bit divider Pn CLK LOAD Pn CLK M 12 4 4 4 Fig. 4. Reference oscillator divider circuit. The implementation of the loop divider demands an additional 4 bit divider block. ARTICLE IN PRESS 28 J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 proportional: Vcontrol V pp / IS  Rpu Vout Vbias Amplitude control VDD Vref Vbias Fig. 5. Ring oscillator topology with amplitude control. VDD C1 M3 − Vout M4 C2 + Vcontrol + V in M1 Vout Vin− M2 Is Vbias M5 (4) where V pp is the peak-to-peak amplitude of the signal at the oscillator core. As a consequence of this dependence, an amplitude control circuit has been added to the core to regulate the tail current, IS , as Rpu varies, in order to maintain an almost constant amplitude value. Capacitors in the differential inverter cells have been implemented by means of accumulation-mode MOS junctions (AMOS) rather than with NMOS transistors. These capacitors must be connected to the positive supply rail in order to avoid the coupling of power-supply noise into the VCO. There is no voltage headroom enough to implement these capacitors using p-channel MOSFETs, and therefore, AMOS capacitors were employed. This kind of capacitors has almost the same capacitance-to-area ratio ðC ox Þ as the MOSFETs, but they work in the accumulation region of the MOS junction (rather than in the inversion region needed by MOSFETs), making them suitable for the voltage values found in the design. This type of capacitor cells usually implement tuning varactors [20], with a nonlinear capacitance–voltage characteristic, causing a nonlinear frequency-to-voltage transfer curve. In our work, however, the tuning is done be means of the linear dependence of the triode load conductance with the voltage (transistors M3 and M 4 in Fig. 6), and therefore, the value of their capacitance is kept constant. Other important reasons to include them instead of other alternatives (such as double poly or metal–insulator–metal capacitors) were their availability in a standard CMOS process and their higher capacitance-to-area ratio. The output of the differential oscillator core resembles a sine wave more rather than a square wave (this point will be shown later in Section 5), and then, a limiter block was added to convert it into a single-ended square wave suitable for clocking purposes. This block is built using a pseudo-differential comparator and a chain of inverters, to saturate the signal to CMOS (rail-to-rail) swing levels and sharpen the square wave edges. 4.3. Phase detector and loop filter Fig. 6. Differential inverter topology used in the VCO design. Table 1 VCO device sizes and loop filter component values VCO device dimensions ðW=LÞ ðmm=mmÞ M 1 and M 2 M 3 and M 4 M5 C 1 and C 2 22/0.35 21/1 15/1 23:6 mm  12:85 mm Off-chip loop filter (discrete) component values R C1 C2 Icp 2:2 kO 220 nF 22 nF 50 mA frequency-to-voltage linearity is also an interesting property of this solution, because of the frequency dependence on the pull-up resistance, Rpu : f0 / 1 Rpu C  mp C ox W C L ðV DD  V control  jV tp jÞ (3) Nevertheless, as Rpu varies, the amplitude of the VCO core generated signal does, because both values are roughly A standard PFD has been implemented along with a charge pump. This kind of phase detector is of extensive use in PLL-based frequency synthesizers [21], and is based on a finite state machine that triggers in the edges of both the VCO and the reference signal. The outputs of the PFD activate the current source or sink, giving positive or negative current pulses to the loop filter. The circuit schematic of the PFD is shown in Fig. 7. The filter circuit is a second order low-pass filter, which smoothes the current pulses given by the charge pump at the output of the PFD. Considering the frequency response of the VCO block, the order of the complete loop rises to 3, and stability becomes an issue as a third pole appears in the transfer function. The designed filter aims for stability in all the operating conditions, and thus, it is designed with a phase margin of FM ’ 60 , which usually gives a good tradeoff between ringing, settling and closed-loop stability [22]. It can be shown that the maximum phase margin is achieved when [23] sffiffiffiffiffiffiffiffiffiffiffiffiffiffi! ! C1 1 (5) FM ¼ arctan þ 1  arctan pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C2 ðC 1 =C 2 Þ þ 1 Choosing C 1 ¼ 10C 2 , the phase margin is FM ¼ 56:44 . The design also comprises the selection of the resistor, R, and the peak current, Icp , sourced or sunk by the charge pump, for a given worst-case K VCO (due to process variations) and divider value. The final filter component values are shown in Table 1, leading to a offchip (discrete) implementation due to the high values required. ARTICLE IN PRESS J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 VDD Ref. 29 350 1.2 Freq. Ampl. 300 1 250 0.8 200 0.6 150 0.4 100 0.2 VCOin Reset Icp Amplitude (V) Icp Frequency (MHz) UP R C2 C1 50 0 1 1.2 1.4 1.6 1.8 2 Control Voltage (V) Fig. 9. Transistor level simulated frequency and amplitude of the differential signal generated at the oscillator core as a function of the control voltage that covers the designed range (96–256 MHz). DOWN VCO Table 2 Transistor level simulated (including layout parasitics) VCO features in the designed (nominal) frequency range (96–256 MHz) Fig. 7. Phase-frequency detector (PFD), charge pump and loop filter. 1.5 V DD ¼ 3:3 V, T ¼ 27  C K VCO f 0 ðMHzÞ Duty cycle (%) V control ðVÞ PN at 100 kHz ðdBc=HzÞ PN at 1 MHz ðdBc=HzÞ Iav ðmAÞ Layout area Differential amplitude (V) 1 0.5 0 -0.5 226:27 MHz=V 256 49.57 1.25 70:18 97:6 3.65 90 mm  150 mm 96 50.06 1.96 62:89 89:9 1.37 amplitude is negligible considering the variations that would appear if no control were employed. In Table 2 the main VCO parameters are summed up, where phase noise simulated values are included for later comparison with experimental data. -1 -1.5 0 2 4 6 8 Time (ns) 10 12 14 Fig. 8. Transistor level simulated steady-state differential waveform at the oscillator core ðf 0 ¼ 256 MHzÞ. 5. Transistor level simulation results Due to the limited output pad number in the test chip, transistor level simulations are presented mainly to show some results that are not available from measurements. In particular, we focus our attention on the VCO block. These simulations were done with the Spectre program using the extracted circuit from the layout. The differential waveform obtained in the oscillator core is drawn in Fig. 8 for the maximum designed oscillation frequency ðf 0 ¼ 256 MHzÞ. The shape of the oscillator output resembles a sine wave, and its amplitude depends of the frequency. Fig. 9 shows both the frequency and amplitude evolution of the VCO core oscillation as a function of the control voltage, V control . The voltage range detailed in the figure covers approximately the nominal design range (96–256 MHz), where the frequency dependence on the voltage is almost linear. In this figure it can also be seen how the amplitude control loop tries to maintain a constant value of amplitude near 1 V. The 20% variation of the 6. Experimental results The test chip was manufactured, encapsulated and soldered into a test board. The layout of the PLL digital section and the VCO is shown in Figs. 10 and 11, respectively, where some functional blocks have been indicated. In Fig. 12 the microphotograph of the complete chip is shown. Without including pads and pin drivers, the active chip area allocated for the PLL is 410 mm  120 mm for the digital section and 90 mm  150 mm for the VCO, totalling 0:063 mm2 , that corresponds to about 3% of the active complete chip area. 6.1. Open-loop VCO measurements Two different measurements were done for the VCO. The V=f characteristic was obtained by using a HP 53131A Universal Frequency Counter, while the phase noise values were measured with a Rohde and Schwarz FSP7 spectrum analyzer by means of a phase noise software module. Fig. 13 shows the V=f characteristic for the measured VCO in the entire operation range, where the transistor level simulated curve has been included for comparison within the nominal design range covering 96–256 MHz. The simulated curve appears centered over the experimental curve because the simulations ARTICLE IN PRESS 30 J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 Fig. 10. PLL digital section layout: dividers, PFD, charge pump, prescaler and shift registers which store the division factors. BP Sigma Delta Modulator LP Sigma Delta Modulator VCO Phase Locked Loop Decimator Fig. 12. Complete chip microphotograph, showing its building blocks. Measured Simulated 600 Frequency (MHz) 500 400 300 200 100 Fig. 11. VCO layout, where some of its building blocks have been indicated. 0 0.5 shown were carried out under nominal process and temperature conditions. Good linearity is achieved in this range, both in simulation and measurement, while the linearity degrades near the upper and lower frequencies, due to both amplitude variations in the core and PMOS loads reaching saturation. Nevertheless, the process variations of the technology cause shifts in the upper and lower frequency values, and thus, in the K VCO . This variation in the VCO gain with respect to nominal values has been accounted for when designing the loop filter for the PLL, in order to meet the worst-case design specifications. Due to the limitation in the number of output pads in the test chip, the VCO output is not directly accessible for measurements. The available waveform for phase noise measurements is a 50% duty cycle clock obtained after dividing the VCO output, as seen in 1 1.5 Control Voltage (V) 2 2.5 Fig. 13. Measured oscillation frequency of the VCO as a function of the control voltage. The transistor level simulated curve is also shown in the 96–256 MHz range for comparison. Fig. 2 (CLK_MON pin). Assuming that the close-in phase noise added by the frequency division is negligible, the output phase noise relates to that of the VCO as [24] LVCO fDf g ¼ Lout fDf g þ 20  log10 N (6) where N stands for the total frequency division factor, with a minimum value of 4 for our design. ARTICLE IN PRESS J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 -10 Table 3 Measured VCO features in the designed (nominal) frequency range (96–256 MHz) -30 321:28 MHz=V 256 1.38 67:93 92:25 3.71 96 1.85 60:95 91:24 1.97 -40 -50 -60 -70 -80 -90 -60 -100 96 MHz 170 MHz 230 MHz 256 MHz -65 -70 -110 1 10 100 1000 Frequency Offset (kHz) -75 Fig. 15. Measured PLL phase noise in locked state for several clock frequencies. -80 -85 -20 -90 -30 -95 -40 -100 0.1 1 Frequency Offset (MHz) Fig. 14. Measured phase noise of the VCO at several frequencies in the 96–256 MHz range. The experimental results obtained at the maximum and minimum frequencies of the designed range are shown in Table 3, while Fig. 14 details the measured phase noise of the VCO at several frequencies in this range. It is worth noting that the phase noise diminishes when the oscillation frequency increases. The main reason for this behavior is the almost constant core oscillation amplitude forced by the control loop, but at the cost of increasing the current consumption. This lowers the thermal noise contribution of the MOS devices and consequently their effective noise figure, lowering phase noise as predicted by Leeson’s formula [25]. A degradation in phase noise, ranging from 3 to 5 dB, is observed between transistor level simulation results and experimental measurements (see Tables 2 and 3). Although the VCO block is shielded by grounded guard rings, the proximity of the frequency divider digital blocks causes the digital current pulses to couple into the VCO ground node. Further transistor level simulations including digital coupling current noise and typical pad impedance values have shown good agreement with the increase in the phase noise observed experimentally. 6.2. Phase locked loop measurements The frequency domain measurements of the PLL were done with the same spectrum analyzer the VCO was measured with. Since in the locked state the previously used CLK_MON pin provides a signal whose frequency is too low for these measurements (5 kHz for the selected 20 MHz reference), another pin was used for measuring clock phase noise. A set of phase noise curves were obtained and shown in Fig. 15. Several frequencies were selected: three from the tuning range of the band pass ADC clock Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) 256 MHz 120 MHz 60 MHz 12 MHz -20 Phase Noise (dBc/Hz) V DD ¼ 3:3 V, room temperature K VCO f 0 ðMHzÞ V control ðVÞ PN at 100 kHz ðdBc=HzÞ PN at 1 MHz ðdBc=HzÞ Iav ðmAÞ 31 Prescaler factor 1 Prescaler factor 2 -50 -60 -70 -80 -90 -100 1 10 100 1000 Frequency Offset (kHz) Fig. 16. Measured PLL phase noise in the locked state operating at 120 MHz for two prescaler values. (12, 60 and 120 MHz), and the last one was 256 MHz (the corresponding clock frequency for the low-pass ADC). The figure shows a good phase noise performance over the designed range, always below the target value of 80 dBc=Hz at 1 MHz offset. There are some issues worth discussing from these measurements. As can be seen in Fig. 15, two regions can be distinguished in the curves: a relatively flat reference noise region, the in-band region, where the frequency response of the loop dominates, and a decreasing frequency region, the out-band region, determined by the open-loop VCO noise. As the operating frequency changes, the in-band reference noise and loop bandwith vary due to the change in the division factor N, according to Eq. (2). When N increases, clock frequency decreases, and more noise amplification occurs in-band. Moreover, the bandwith of the loop decreases. Both effects are observed in the measurements shown in Fig. 15. In the out-band region, the PLL phase noise is determined by the VCO phase noise, and then, since the VCO is working at different frequencies, with different power consumptions, different PLL phase noise curves are measured. Moreover, the presence of the prescaler adds another degree of freedom to the block design. Since the clock is obtained just after the prescaler (Fig. 2), the locked state frequency value is ARTICLE IN PRESS 32 J. Segundo et al. / INTEGRATION, the VLSI journal 42 (2009) 24–33 Table 4 Measured PLL current consumption, showing separately the VCO and digital section consumptions Clock freq. (MHz) 12 60 120 256 Prescaler value VCO freq. (MHz) IVCO (mA) Idigital (mA) IPLL (mA) 8 2 1 1 96 120 120 256 1.97 2.30 2.30 3.61 0.205 0.551 0.935 1.953 2.175 2.851 3.235 5.563 A 3:3 V supply voltage was used. independent of the prescaler value, and depends only on the loop divider value, provided the VCO is running in the 96–256 MHz range. In consequence, different prescaler values can be chosen in order to synthesize the same clock frequency. The phase noise obtained for the 120 MHz clock with two different prescaler settings is shown in Fig. 16. As it can be clearly seen, the clock operating with the higher prescaler value overperforms the other in the out of band region of the PLL. A higher prescaler value makes the VCO run at higher frequency, dissipating a higher power, but with lower phase noise. In the in-band region, the PLL operating in locked state filters the reference noise, and therefore, similar noise values are achieved. Finally, some details about the PLL power consumption can be discussed. The current drawn from a 3.3 V supply voltage at several clock frequencies is detailed in Table 4. As can be seen, most of the overall power consumption is due to the VCO, increasing when the VCO output frequency does. The current consumption of the digital CMOS circuitry (dividers, flip-flops, etc.) is mainly determined by their operating frequency, which depends on the desired output clock frequency and prescaler settings. The power consumption of the VCO is directly related to its phase noise via several mechanisms. First, the architecture of the inverter cell (e.g., differential vs. single-ended) determines the capability of rejecting common-mode noise. A single-ended inverter cell should reduce the power consumption at the expense of increasing phase noise. Second, a tradeoff between power consumption and phase noise can be found through the value of V ref in the amplitude feedback loop (see Fig. 5). Higher amplitudes tend to decrease the phase noise (because of the boost in signal power and steepness in the zero crossings), while the current consumption also increases as needed to keep the Rpu  IS product in the desired value. Finally, in order to cover all the technology corners and a wide temperature range a conservative design procedure was adopted, and then, a relatively higher power consumption was obtained. As the experimental phase noise overperforms the target phase noise spec for our application, future designs can be carried out according to a more aggressive design approach. 7. Conclusions The design and implementation in a 0:35 mm CMOS technology of a PLL-based tunable clock synthesizer has been presented. The suitability of this solution for the clocking of two continuous-time SD ADCs (also included in the designed chip) has been analyzed, together with the problems and constraints derived from clock jitter. The requirements for the clock synthesizer have been extracted from the frequency specs and system level simulations for our application. In particular, the impact of clock phase noise on the CT SD modulators and the PLL design tradeoffs have been discussed. A third order phase locked loop approach has been selected, with a tunable output frequency of 12–256 MHz with a minimum PLL tuning step of 10 kHz. A differential ring-based VCO has been used, with good linearity and phase noise below 90 dBc=Hz for all the frequencies of interest. Transistor level simulations have been carried out to show significant VCO waveforms nonexperimentally available, and to verify that specs are satisfied by the chosen circuit implementation. PLL experimental results show good agreement with simulations. The complete clock generation circuitry achieves a phase noise better than the target spec of 80 dBc=Hz at 1 MHz offset required for our modulators in the entire tuning range, with a current consumption ranging from 2.2 to 5.6 mA drawn from a 3.3 V supply voltage. References [1] T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, 2004. [2] J. Crols, M. Steyaert, CMOS Wireless Transceiver Design, Kluwer Academic Publisher, Dordrecht, 1999. [3] S.R. Norsworthy, R. Schreier, G.C. Temes, Delta–Sigma Data Converters: Theory, Design and Simulation, IEEE Press, New York, 1997. [4] J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J.S. Pablo, L. Quintanilla, J. Barbolla, A 32 mW 320-MHz continuous-time complex delta–sigma ADC for multi-mode wireless-LAN receivers, IEEE J. Solid-State Circuits 41 (2) (2006) 339–351. [5] J.A. Cherry, W.M. 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Jokin Segundo received the Ingeniero en Telecomunicación degree in 2005 and the Ingeniero en Electrónica degree 2006, both from the University of Valladolid, Spain. In 2006 he joined the Departamento de Electricidad y Electrónica, University of Valladolid, where he works as an assistant professor in Electronics. He is nowadays working toward his Ph.D. and his current research interest are in the field of analog and mixed-signal design, specially high-speed A/D converters for communication systems. Luis Quintanilla received the Licenciado en Fı́sica degree in 1991 and the Ph.D. degree in Sciences (Physics) in 1993 both from the University of Valladolid, Valladolid, Spain. He joined the Departamento de Electricidad y Electrónica, University of Valladolid, in 1993 where he is now a professor in Electronics. He has been working in electrical characterization of semiconductor materials and devices and his current research interest is the design of analog/digital converters for communication systems. Jesús Arias received the Licenciado en Fı́sica degree in 1989 and the Ph.D. degree in Sciences (Physics) in 1995, both from the University of Valladolid, Valladolid, Spain. In 1989 he joined the Departamento de Electricidad y Electrónica, University of Valladolid, where he is now a professor in Electronics. He has been working in electrical characterization of semiconductor materials and devices, including computer simulation of semiconductor processing. His current research interest is the design of analog/digital converters for communication systems. 33 Lourdes Enrı́quez received the Licenciado en Fı́sica degree in 1989 and the Ph.D. degree in Sciences (Physics) in 1995, both from the University of Valladolid, Valladolid, Spain. In 1989 she joined the Departamento de Electricidad y Electrónica, University of Valladolid, where she is now a professor in Electronics. She has been working in electrical characterization of semiconductor materials and devices, and her current research interest is the design of analog/digital converters for communication systems. Jesús M. Hernández-Mangas received the Licenciado en Fı́sica and the Ingeniero en Electrónica degrees in 1993 and 1995, respectively, from the University of Valladolid, Valladolid, Spain. He also obtained the Ph.D. degree in Sciences (Physics) from the University of Valladolid, Valladolid, Spain, in 2000. He joined the Departamento de Electricidad y Electrónica, University of Valladolid, in 1994, where he is now a professor in Electronics. He has been working in computer simulation of semiconductor processing. His current research interests are the design of analog/ digital circuits for low power, low voltage and highspeed applications. José Vicente was born in Zamora, Spain, in 1953. He received the Licenciado and the Ph.D. degree in Physics, both from the University of Valladolid, Valladolid, Spain, in 1977 and 1981, respectively. He holds both research and teaching positions in the Electrical and Electronics Department at the University of Valladolid. He has been working in the characterization of devices and deep levels in semiconductors. He has experience in technology process development, including diffusion and modeling of recombination centers in silicon and design of oscillators. His current research interest is the design of analog/digital converters for communication systems.