INVITED PAPER Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Studies of noise activity, in chip substrates that are shared by digital and analog circuits, are aiding efforts to reduce crosstalk and to model noise isolation schemes. By Ali Afzali-Kusha, Senior Member IEEE, Makoto Nagata, Member IEEE, Nishath K. Verghese, Senior Member IEEE, and David J. Allstot, Fellow IEEE ABSTRACT | Issues related to substrate noise in system-on- chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed. KEYWORDS | Boundary element methods; digital switching noise; finite-difference methods; integrated circuit noise; mixed analog-digital integrated circuits; network reduction methods; noise; noise generators; signal integrity; substrate coupling; substrate noise measurement; switching circuits I. INTRODUCTION The push for lower cost, smaller size, and more features has motivated the combining of analog circuits with digital Manuscript received September 1, 2005; revised September 21, 2006. The work of A. Afzali-Kusha was supported by the Research Council of The University of Tehran. The work of D. J. Allstot was supported in part by the National Science Foundation under Contract CCR-0086032 and in part by Semiconductor Research Corporation under Contract 2006-HJ-1427. A. Afzali-Kusha is with the Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran (e-mail: afzali@ut.ac.ir; afzali5@gmail.com). M. Nagata is with the Department of Computer and Systems Engineering, Kobe University, Kobe 657-8501, Japan (e-mail: nagata@cs.kobe-u.ac.jp). N. K. Verghese is with Clear Shape Technologies, Santa Clara, CA 95054 USA (e-mail: nashv@clearshape.com). D. J. Allstot is with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA (e-mail: allstot@u.washington.edu). Digital Object Identifier: 10.1109/JPROC.2006.886029 0018-9219/$20.00 Ó 2006 IEEE subsystems. As CMOS technology scales, digital circuit speed, analog resolution, chip packing density, and the number of interconnect layers are increased in these mixed-signal systems. Wireless applications also flourish wherein radio-frequency (RF) analog circuits are integrated with baseband digital circuitry to realize system-on-chip (SoC) solutions; in fact, the single-chip transceiver in CMOS is a reality [1]. A key advantage of SoC integration is lower power for portability due to fewer package pins with less bond-wire capacitance. Power is also saved because fewer high-frequency signals that require 50-
interfaces are routed off chip. Overall system performance and reliability are improved due to reduced interconnect and package parasitics, smaller package count, and the higher integration level. The design of SoC systems is complicated. One challenge, specific to RF integrated circuits, is to implement high-quality on-chip passive elements such as high-Q inductors [2]. A daunting challenge is to minimize deleterious noise (undesired signal) coupling between on-chip circuit blocks [3], [4], i.e., it must be predictable and controllable. A mixed-signal chip typically comprises both sensitive analog/RF circuits and high-swing high-frequency noise-injecting digital blocks with coupling between them via the power grids and the common conductive substrate. Moreover, CMOS technology scaling reduces the distance between them which exacerbates the problem. Noise coupling is a potential show-stopper for SoC integration; undesired signal interactions limit performance even as higher clock rates and greater precision are demanded. A simple example illustrates the severity of the problem: an RF signal typically ranges from
120 dBm (0.22
V RMS ) to 20 dBm (2.24 V RMS ) in a 50-
system [5], [6]. At the lowest signal levels, RF circuits are sensitive to intrinsic device noise let alone coupled substrate noise. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2109 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation The coupling of digital switching noise to sensitive analog circuits is depicted in Fig. 1. The shared silicon substrate is one important medium through which it (Bsubstrate coupling[ or Bsubstrate noise coupling[) occurs. A digital state transition causes fluctuations in the underlying voltage that spread through the substrate and cause substrate potential variations at sensitive analog/ RF devices. Crosstalk between high-frequency/high-power analog outputs and sensitive analog/RF devices is another coupling mechanism. The coupled noise is typically weak, but it can degrade the performance of sensitive input amplifiers, local oscillators, etc. [7]. Signal leakage (current injection) into the conductive substrate also leads to power loss in RF circuits. Finally, noise coupling is not restricted to the shared substrate and power grids. Other coupling media include the parasitics between on-chip interconnect layers, external bondwires, package pins, board traces, etc. In general, noise coupling occurs between aggressors and victims within a block (interblock) or between blocks (intrablock). State-of-the-art techniques to model, analyze, and control noise coupling in mixed-signal systems are presented in this paper. Distinctions between device random noise and deterministic digital switching noise are drawn in Section II. The physical phenomena responsible for the generation of digital switching noise and its transport through the substrate are described. Section III covers the modeling and simulation of digital switching noise and the development of passive lumped-element networks that couple aggressors and victims via the substrate. Design engineering practices that minimize noise coupling are reviewed in Section IV, and measurement-based studies of various chip-level substrate noise analyses and noise reduction schemes are given in Section V. Fig. 1. Power supply grid and substrate noise coupling in a mixed-signal SoC [8]. 2110 I I. MECHANISMS AND E FFECTS OF MIXED-SIGNAL NOISE COUPLING A. Random versus Deterministic Noise All undesired phenomena, behaviors, or influences that degrade the performance of a system are regarded as noise [8]. Noise is of two types in a mixed-signal IC: noise of active and passive devices (thermal noise, shot noise, flicker noise, etc.) and extrinsic noise (digital switching noise, crosstalk, etc.). Random device noise is a fundamental limitation in analog circuits as it defines the minimum detectable signal level. It is minimized by proper process, device, circuit, and topology selections, and optimum bandwidth design. It is often treated as an inputreferred noise source as determined from circuit noise analysis, and quantified using the noise figure (NF) and signal-to-noise ratio (SNR) parameters. In contrast to random noise signals, digital switching noise, coupled high-frequency analog signals, etc., are deterministic and can, therefore, be quantified in both the frequency and time domains. In practice, digital switching noise is the dominant source of deterministic noise in mixed-signal chips [6]. It is deleterious because it can be coupled over long distances through the substrate to sensitive analog transistors where it modulates their threshold voltages, gains, etc. It also increases the propagation delays of sensitive digital blocks [9]. B. Coupling From Digital Integrated Circuits Digital switching noise stimulates the substrate via several mechanisms including direct injection of impact ionization currents at the device level, capacitive coupling of displacement (charging/discharging) currents at the circuit level, and ohmic coupling of power supply/ground noise voltages at the chip level. Their relative magnitudes are determined from substrate noise measurements that include detailed waveforms with distinctive physical properties. Substrate noise voltage waveforms measured using an on-chip probing technique with 100 ps and 100
V resolutions are shown in Fig. 2 [10]. The results correspond to bursts of pulses applied to 32 noise source units (NSU) where each NSU comprises 30 0.3-
m CMOS static inverters connected in parallel. The time intervals ðT s Þ between rising/falling transitions in Fig. 2(a) and (b) were 2 and 9.3 ns, respectively. The positive voltage peaks induced synchronously with the clock edges correspond to digital switching noise that is coupled to the p-type bulk via ohmic substrate contacts, i.e., power supply/ground bounce is the dominant source of substrate noise as evidenced by the absence of negative peaks. With T s ¼ 2 ns, the individual events are merged into a single large long peak, but with T s ¼ 9:3 ns the switching peaks are clearly separated. Additional data (Fig. 3) shows an approximate linear dependence of peak noise amplitude on the number of NSUs. The direction dependence arises from charging Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation impedances associated with the power grid networks [15]. A power bus line exhibits distributed capacitance to the substrate plus distributed series inductance and resistance; there is also mutual capacitance and inductance between lines. Parasitics associated with external ports (bond wires, package pins, board traces, etc.) are typically modeled as lumped-element series inductances and resistances. A CMOS inverter with equivalent power grid and external port parasitics (not including coupling capacitances to the package cavity) is shown in Fig. 5 [6]. The BV DD bounce[ and BGnd bounce[ noise voltages are given by Vdrop ¼ Ri þ L Fig. 2. Measured substrate noise waveforms from transition controllable noise source with stage delays of (a) Ts ¼ 2:0 ns and (b) Ts ¼ 9:3 ns. currents that are unequal due to asymmetric parasitics associated with the N-well process, i.e., the NþP-substrate capacitance near Gnd is less than the PþN-well parasitic near V DD . These issues are revisited in Section V-B. Displacement currents are injected into the substrate during state transitions of digital circuits through source/ drain junction capacitances, and by high-frequency signals on N-wells and interconnect lines through reverse-biased N-well/P-substrate diodes and overlap capacitances, respectively. They become increasingly important with technology scaling as both the number of digital switching nodes and interconnect capacitances increase. The injection of displacement current was demonstrated using a large CMOS inverter capacitively coupled to the substrate and strategically placed single-transistor NMOS current source detectors [11]. The drain current fluctuates due to substrate noise voltage that is resistively coupled to the back-gate region and capacitively coupled from there to the other NMOS terminals. Substrate noise due to capacitively coupled displacement current exhibits both positive and negative voltage peaks for rising and falling transitions, respectively, as shown in Fig. 4. Noise is also created when impact ionization current is injected into the substrate which occurs when the electric field in the drain-bulk depletion region is sufficient to create electron-hole pairs. It can be transported through the substrate to other regions of the chip even under static conditions. It is insignificant in older technologies but should be considered in deep-submicron CMOS processes in certain situations [12], [13]. In general, however, it remains negligible because power supply/ground bounce noise and capacitive coupling increase with scaling [14]. C. Effects of the Power/Ground Grids and Package/ Bondwire Parasitics on Noise Generation Power supply/ground bounce noise voltages are created when displacement currents flow through the parasitic di dt (1) where R and L are relevant parasitics. The terms denote resistive and inductive voltage drops that are proportional to the switching current and its first derivative, respectively. The second term, known as Binductive noise,[ BLðdi=dtÞ noise,[ and Bdelta-I noise[ also creates ringing in the parasitic RLC networks associated with power supply rails and output drivers [6], [11], [16]–[18]. Hence, not only are the V DD and Gnd grids not at their ideal voltages, switching noise is distributed through them to sensitive circuits in remote regions of the chip. If the same ground grid also supplies the substrate bias, ground bounce propagates directly to the substrate through ohmic contacts and parasitic junction capacitances. These effects explain the substrate noise voltages shown in Fig. 2. The ringing is more pronounced in Fig. 2(a) because T s is smaller, and hence, di=dt is effectively larger than in Fig. 2(b). The peak substrate noise voltage amplitude increases if parasitic capacitance is decreased so that di=dt Fig. 3. Measured substrate noise peak amplitudes versus number of activated noise source units. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2111 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 4. Capacitively coupled noise from single CMOS inverter [11]. increases; but, it decreases if added parasitic capacitance acts as decoupling capacitance for the supply networks [19]. The latter effect occurs as follows. If, for example, a CMOS inverter is inactive (i.e., not switching) with its output HIGH (LOW), its total load capacitance is connected to the V DD (Gnd) power grid through its lowimpedance PMOS (NMOS) pull-up (pull-down) device. In Fig. 6(a), the relative reduction in peak noise amplitude Fig. 5. Noise coupling from switching portion of an IC to RF/analog portion via substrate. Some parasitic elements involved in undesired signal coupling are shown [6]. 2112 Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 6. Effects of parasitic capacitances on noise amplitude. Number of inactive logic cells increases in curve (a), while position of fixed number of inactive logic cells moves away from active logic cells in curve (b) [19]. versus Nres/Nact is plotted where Nres is the number of inactive gates in the cell row (gray area) that are, in (a), immediately adjacent to Nact ¼ 320 active cells fixed at one end of the row (black area) [19]. The white cell row regions contain Binvisible logic cells,[ i.e., gates that are disconnected from both the V DD and Gnd power grids via OFF series PMOS and NMOS devices, respectively. The noise decreases as the number of adjacent inactive logic cells increases because of the effective increase in decoupling capacitance. In Fig. 6(b), the relative reduction in peak noise amplitude versus Nsep/Nact is plotted where Nsep is the number of invisible gates in the cell row (white area) that are, in (b), between Nact ¼ 320 active cells on the right (black area) and Nres ¼ 320 inactive cells to the left (gray area) [19]. The noise reduction deteriorates as the inactive cells move farther from the active cells due to increases in the power supply/ground rail impedances. The mutual capacitances and inductances between bond wires, package pins, and board traces also cause noise coupling; moreover, larger parasitics are usually associated with cheaper packages [20]. D. Coupling Through the Substrate Medium Digital switching noise couples through the shared substrate to sensitive circuits. The degree of coupling among various silicon processes depends on device type (BJT, NMOS, PMOS, etc.) [21], [22] and wafer type/ structure (bulk, epitaxial, SOI, etc.) [12]. Coupling intensity is also a strong function of impurity profiles and guard-ring/isolation techniques. In [23], different isolation schemes to minimize substrate crosstalk are compared and lumped-element models are developed for use in circuit simulation. They are validated by device- and circuit-level simulations and experimental results measured under small-signal operation; the scattering parameter, s21 , is used as a quantitative measure of isolation. The aggressor was a 50  50
m NMOS device and the victim/sensor was a 50  50
m p-well contact located at a fixed dis- tance [Fig. 7(a)]. The doping profiles used in the devicelevel (MEDICI) simulations were for a 0.8-
m BiCMOS process with an initial substrate resistivity of about 6
cm. As shown in Fig. 7(b), a significant decrease in crosstalk is achieved using any of the isolation techniques. But, the best result is obtained using a non-mainstream technologyVan SOI wafer with pþ guard-ring and deeptrench isolations and with a grounded handle (base substrate). Note that when the supporting substrate is grounded, isolation is increased in either bulk or SOI technologies, but pþ guard rings have little impact. For the BiCMOS substrate of Fig. 7(a), the noise propagates laterally through the deep pþ buried layer and is largely unimpeded by n-well guard rings. Substrate crosstalk increases with frequency in all cases because the isolation impedances decrease as ð2fCÞ
1 . Thus, although an SOI process provides superior isolation at lower frequencies its benefit disappears at higher frequencies as determined by the buried oxide thickness, effective areas of the aggressor and victim circuits, etc. Techniques to reduce substrate coupling are further detailed in Section IV-C. The frequency behavior in Fig. 7(b) suggests that lumped-element RC circuits may be used to model the Fig. 7. (a) Schematic representation of crosstalk noise generated by pulsing a MOSFET. Arrows represent current flow paths and Rp is a parasitic series resistance. Voltage drop due to the current transition is felt throughout the Si substrate. (b) MEDICI simulation results [23]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2113 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation isolation schemes. In addition, a general substrate noise analysis capability provides a visual profile of the noise amplitude at each location on a chip induced by a single noise source or a mapping of the coupling strength from each noise injection point to each sensitive analog/RF node. E. Coupling to Analog/RF Integrated Circuits Coupling is a problem in pure analog/RF circuits wherein the substrate provides a parasitic feedback path that adversely affects amplifier small-signal gain, bandwidth, stability, etc. [5]. The substrate also facilitates noise coupling across a chip because it acts as the collector, integrator, and distributor of digital switching currents [5], [24]. An analog/RF device senses substrate noise via variations in its back-gate potential (body effect) or by coupling through its junction/overlap parasitic capacitances. Consequently, noise spikes are induced in its output current and voltage. Examples of the effects of digital control pulses on the behavior of an operational amplifier are presented in [25]. As substrate doping density increases according to scaling trends, noise coupling via the body effect becomes less important than that through depletion capacitances [21]. Note that passive devices such as diffused resistors and precision polysilicon or MIM capacitors also sense noise via parasitic capacitive coupling to the substrate [13]. The effects of digital switching noise on a highresolution oversampling A/D converter integrated in a 1-
m CMOS process with a p-type epitaxial substrate are presented in [26]. The modulator was a third-order cascade of a second-order stage followed by a first-order stage; both stages use 1-bit quantizers. It exhibits a dynamic range greater than 100 dB over the 20-kHz digital audio bandwidth. A test circuit was integrated with it to emulate embedding it with a large amount of active digital circuitry on a common substrate. High sensitivity to the timing between the analog signal sampling and noisy digital clock edges is observed, and severe degradation occurs when they transition simultaneously. Specifically, harmonic distortion products of the input signal appear over the entire bandwidth of the modulator. Techniques to model and analyze substrate noise coupling in pipelined A/D converters are also presented in a study that compares the effects of substrate type (lightly or highly doped) and noise shielding methods on performance [27]. On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing SoCs. But, the presence of partially correlated substrate noise presents a new challenge in predicting PLL jitter [28], [29]. Timing jitter due to substrate noise coupling noise is estimated using a cyclostationary approach in [28]. In [29], a stochastic model of the substrate and power supply/Gnd grid noise sources is used to calculate the phase noise of the constituent voltage-controlled oscillator (VCO), from which the PLL timing jitter is predicted. The impact of clock jitter 2114 induced by substrate noise on the performance of an oversampling delta-sigma modulator is reported in [30]; it is shown that the SNR of the modulator is degraded and, more important, that noise shaping does not reduce the effects of the substrate noise clock jitter component. Noise coupling into an analog phase-locked loop is analyzed for three different power grid configurations in [31]. The study reports jitter measurements of identical PLL circuits integrated with digital switching blocks on a shared low-resistivity substrate. It is shown that power supply/Gnd grid noise coupling occurs by a different mechanism in each of the three PLLs. For the first PLL that shares both its V dd and V ss (Gnd) grids with the digital switching blocks, the dominant jitter source was supply coupling into its VCO. When separate V dd and V ss grids are used in the second PLL, noise couples into the loop filter node because parasitic resistance in the epitaxial layer effectively provides a second input from the substrate to the loop filter capacitor. The third PLL with separate V dd grids but a shared V ss network exhibited much less jitter than the other PLLs. In this case, delay variations in the feedback divider are the primary source of jitter, and the mixing of them with the PLL reference frequency creates low-frequency tones. If the beat frequency is lower than the PLL bandwidth, the PLL tracks it. This occurs only when a harmonic of the digital switching noise is near the PLL reference frequency. The same PLL fabricated in a triple-well process demonstrates that noise injection into the loop filter and the coupling of digital switching harmonics are eliminated. The importance of keeping the triple-well area small to minimize capacitive coupling at high frequencies is also presented [31]. The analysis of substrate noise coupling in an industrial PLL with approximately 1800 transistors fabricated on a 0.72-
m process with an epitaxial heavily doped bulk substrate is presented in [32]. A noise generator consisting of five output buffers in series resides near the PLL. The sensitive circuitry is surrounded by both ohmic and n-well guard rings. Six different structures are used to compare various guard-banding techniques: a backplane contact with no guard ring, pþ guard ring, pþ guard ring with a backplane contact, ohmic guard ring in the VCO, and both ohmic and pþ guard rings in the VCO. A single pþ guard ring is placed around the entire analog section; the ohmic guard ring consists of many ohmic guard bands placed as close as possible to all sensitive devices not in well regions. The results show that well guard-ring structures are not useful for noise reduction, and the effectiveness of ohmic guard rings depends on their number, locations in the layout, and biasing details. The best isolation is obtained using a pþ guard ring and the backplane contact, with a separate bias for the guard ring. If the same bias grid is used for the guard-ring structures as for the digital circuits, the measured jitter increases dramatically. A model to predict substrate switching noise generation and propagation and the resulting analog/RF performance Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation degradation is presented [33]. Measurements on a mixed-signal IC with a 40K-gate digital data path and an LC-VCO in a 0.18-
m CMOS process with a lightly doped substrate are also reported. Substrate coupling is catastrophic in high-frequency analog circuits where on-chip interferers due to substrate noise and undesired mixing products are larger than the desired carrier signal. Substrate coupling to a sensitive node from planar spiral inductors at radio frequencies via oxide capacitance is reported in [34] and [35]. A heavily doped bulk substrate is considered and both experimental and simulation results are presented. Hollow inductors exhibit less substrate noise because of their smaller oxide parasitic capacitance. The results also indicate that inductor-induced noise is a potential obstacle to integrating an RF power amplifier with sensitive receiver circuits on the same die. A guard ring placed near the inductor is ineffective because of the mirror effect which dramatically reduces its inductance. A segmented guard ring is employed to reduce the eddy current flow in the substrate [36], [37]. Substrate coupling may cause spurs (undesired frequency tones) within the frequency band of an RF system. Specifically, intermodulation (IM) of the noise components with a carrier signal and direct coupling of the substrate noise create spurs. Substrate coupling also leads to frequency modulation effects in an oscillator that increases its output phase noise. The strengths of the spurs induced by both mechanisms can be comparable and no more than 60 dB below the carrier power, which is problematic in the design of a receiver [36], [38]. As the dynamic range of an RF receiver should be wide, the sensitivity of every internal node to substrate noise coupling should be carefully assessed. A fully extracted transistor-level circuit netlist of the analog/RF circuit (VCO, LNA, etc.) along with a substrate network model can be used for nonlinear time-domain circuit simulations. A Fourier transform spectrum analysis of the resulting output waveform may be used to determine the relative contributions of individual active devices in the creation of spurs. Periodic small-signal analysis is a fast computational method to determine the sensitivity of an output signal at a given frequency to noise signals injected at various points in the substrate [6]. The sensitivity strongly depends on the symmetry in the layout of the circuit as well as the vertical substrate structure. It has been shown that common-mode coupling can cause significant IM spurs even in a fully differential design [6]. II I. MODELING OF MIXED-SIGNAL NOISE COUPLING A substrate noise analysis technique must include circuit simulation to assess the impact of substrate noise on a particular parameter of interest for a specific analog/RF function. Hence, analysis requires an equivalent circuit model for the substrate to be used with the circuit. Extraction is the process by which an RC equivalent circuit of the substrate is determined. To accurately extract it, the complex geometries of wells, well taps, substrate contacts, diffusions, trenches, etc., must be considered. Once the extraction is finished, simulation is performed on the complete circuit including the extracted RC equivalent circuit of the substrate. Some devices behave as aggressors and others act as victims with the substrate as the coupling medium. The advantage of using circuit simulation (e.g., SPICE) for substrate noise coupling analysis along with proper models of the substrate is that there is no need for separate modeling of the noise injectors and receptors. However, the required computation time, with active and passive devices and equivalent substrate RC models, explodes quickly and limits its use to relatively small circuits. For larger circuits, one may use macromodels of the substrate and aggressor circuits. Various approaches to substrate modeling are presented in the following. A. Modeling Coupling to Substrate 1) Modeling Noise Injection to Substrate: In order to model the effects of coupling, expressions or equivalent circuits must first be incorporated into a circuit simulator to calculate the currents and voltages injected into the substrate. Important device capacitances are included in transistor models for SPICE-like circuit simulators. In the case of interconnect-to-substrate capacitances, however, the layout must be extracted in order to determine them. As the values are layout dependent, they are extracted after the layout is complete and are typically incorporated in the simulator for postlayout simulations. The contribution of impact ionization is included in the noise current models employed by SPICE. For example, in one of these models the hot-electron-induced substrate current is expressed in semi-analytical form as [39] 1=2 Isub C2 t1=3 ox  xj ¼ C1 ðVds
Vdsat ÞId exp
Vds
Vdsat ! (2) where C1 and C2 are process-related empirically determined parameters, tox is the oxide thickness, xj is the junction depth, Vds is the drain-to-source voltage, and Vdsat is the saturation voltage. Using device-level simulations or measurements results, it is possible to determine the empirical coefficients, C1 and C2 , and incorporate them for circuit simulation. The straightforward approach discussed here can provide good accuracy in modeling the noise current. As discussed before, one of its major drawbacks is that simulations of large circuits require impractical amounts of memory and computation time. The use of macromodeling-based simulators with a higher level of Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2115 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation abstraction than the transistor-level descriptions in SPICE can accelerate the computations and increase the maximum size of simulated circuits that can be simulated. These enhanced SPICE-like simulators can simulate an entire large-scale digital circuit using an extracted netlist. They are capable of simulating hundreds of thousands of components through the use of device macromodels based on table look-up I-V characteristics and hierarchical circuit macromodels that rely on similar operation among primitive circuits with the same set of input signals. Next, macromodeling methods for large-scale digital blocks are described. 2) Noise Current Macromodels: A traditional idea of macromodeling assumes that when a logic gate toggles, it draws current with a triangular waveform where the height and slope of the triangle depend on the logic function and the fanout load capacitance. When both of these features are known in advance, the power supply current of a digital circuit for a given input vector can be approximated by superimposing such triangular currents. For noise analysis, one can use the captured noise current directly for calculating electromagnetic radiation and power supply/Gnd bounce noise characteristics [40]. The power supply/Gnd grid noise characteristics are obtained using their network impedance parasitics. The noise current also may be used for determining injection into the substrate. This allows the substitution of transistorlevel circuit simulation by gate-level logic simulation for greatly improving simulation speed and the size of the circuit that can be handled in the noise analysis. Another approach for modeling switching current sources utilizes the concept of a substrate noise signature for each digital gate [41], [42]. This methodology exploits the fact that any given logic gate injects a particular signal into the substrate through capacitive coupling and impact ionization. Such a signal, known as the substrate injection pattern, is a unique fingerprint of the gate, input transition, circuit implementation, and technology. It can be accurately calculated using standard device modeling and circuit simulation techniques, and it is more accurate than the simple signature obtained using the triangular waveform approximation described previously. The substrate noise signature of the entire circuit is then evaluated using the substrate injection patterns and a precise analysis of the switching activity at the internal nodes of the circuit. The switching activities are computed from user-specified input vector sequences by a gate-level simulation. Since the input vector is not known a priori, the user should simulate a realistic set of input vectors and perform worst/ best case analyses. Improvements to this approach are discussed in [43] where the power supply current flowing from Vdd to Gnd and the noise current injected directly into the substrate are separately characterized for every digital gate with every possible input combination and stored in a standard cell library as auxiliary information. 2116 Fig. 8. Time-series divided parasitic capacitance (TSDPC) model [44]. The pairs are then combined in synthesizing the substrate noise current according to the switching activities. In contrast to the previous signature-based techniques that approximate a noise current by the superposition of predetermined waveforms, the time-series divided parasitic capacitance (TSDPC) method substitutes a single capacitor charging process for a large collection of logic transitions that occur in some time interval [44]. A bank of switched capacitors (Fig. 8) represents a large-scale digital circuit for simulating the power supply currents; the capacitances are derived from the toggle records obtained by a gate-level logic simulation. A circuit-level simulator then determines the power supply current through a charge transfer process within digital circuits where parasitic impedances are included. This improves the accuracy of the noise currents and the power supply/Gnd bounces that are coupled to the substrate. B. Modeling Substrate Parasitics Due to its distributed nature, the substrate cannot be translated into a compact analytical model accounting for the entire chip area whose global effects are felt everywhere in the chip. In general, the models for the substrate coupling can be derived from a full 3-D numerical simulation using either a suitable discretization of a simplified form of the Maxwell’s equations or lumped-element models. Common techniques to model the substrate include the finite-difference method (FDM) followed by a network reduction of the resulting mesh or the boundary element method (BEM) followed by fast BEM matrix solution techniques. 1) Box Integration Formulation: To obtain a distributed RC network, the box integration technique may be utilized [45]. In this approach, a 3-D rectangular RC mesh network is constructed as an equivalent circuit representation of the modeled substrate. The mesh topology may be correlated to the physical design of the circuit by distributing the grid points according to the layout features on the relevant fabrication photomasks. The substrate is treated as a 3-D mesh where each mesh edge represents a parallel Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation combination of a resistor and a capacitor. The edge surfaces are assumed to be Neumann (reflective) boundaries for voltages whereas the diffusion/active regions and contact areas are treated as Dirichlet (fixed) boundaries for voltages (equipotential regions) in the resulting 3-D RC mesh. These areas are represented as ports in the multiport network and connected to corresponding nodes in the electrical circuit [46]. Outside the diffusion/active areas (i.e., the ports), the substrate can be approximated as layers of uniformly doped semiconductor of varying doping density. In these regions, a box integration method [47] can be applied to spatially discretize the simplified Maxwell’s equations. Ignoring the magnetic field and using the identity r  ðr  AÞ ¼ 0, Maxwell’s equation can be written as rJþr @D ¼0 @t (3) where J is the current density, D is the displacement vector, and t is time. Using the relations D ¼ "E and J ¼ E yields r  E þ " @ ðr  EÞ ¼ 0 @t (4) where E is the electric field,  is the conductivity, and " is the permitivity. The equation can be discretized on a substrate volume either in differential form using FDM or integral form using BEM as explained later. In the FDM technique, the substrate is represented as a collection of square cubes as shown in Fig. 9 [18]. An electric field normal to a contact plane of two adjacent cubes ði; jÞ with distance hij is given by Vi
Vj : Eij ¼ hij (5) Fig. 9. Substrate modeled as a collection of square cubes [7]. and   wij  dij Cij ¼ " hij (8) as shown in Fig. 10. This approach is not efficient because large 3-D meshes are created which are prohibitive to simulate using variable time-step trapezoidal integration techniques. As an example where this approach is inefficient, consider the case of a lightly doped substrate where much empty space (between ports) must be discretized to obtain an accurate estimate of the port-to-port substrate admittance [24]. 2) Network Reduction: To address this problem, the generated linear RC network should be approximated by a smaller circuit that exhibits similar electrical properties. Using Gauss’s law under the assumptions of a uniform impurity concentration in the cube and applying the box integration method, (4) may be rewritten as [7], [47] X j Gij ðVi
Vj Þ þ Cij  @ @ Vi
Vj @t @t  ¼0 (6) where   wij  dij Gij ¼  hij (7) Fig. 10. Resistances and capacitances around a mesh node in electrical substrate mesh [7]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2117 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation A small percentage of the network nodes are physically connected to the external circuit (at the top surface of the substrate). In theory, an Bequivalent[ multiport network (similar to a Thevenin equivalent circuit for a one-port network) can be obtained by eliminating a substantial fraction of the internal nodes [45]. This technique is generally referred to as Bnetwork reduction.[ For network reduction using congruence transformations [45], fullnetwork conductance and susceptance matrices are transformed to reduced equivalent models that can be directly realized with resistors and capacitors. This algorithm utilizes the well-conditioned symmetric Lanczos process, which exploits the specialized structure of extracted substrate networks to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability and create reduced networks that are easily realizable with RC elements. The approximate networks are guaranteed to be passive and are thus well behaved in subsequent simulations. The reduced models retain the accuracy of original models but contain orders of magnitude fewer circuit nodes. The network reduction problem can be simplified if capacitances in the RC mesh can be ignored. Neglecting the intrinsic substrate capacitance is a reasonable assumption for operating speeds of up to a few gigahertz and switching times less than about 100 ps. This is due to the fact that the relaxation time of the substrate (outside of the active areas and well diffusions) which is given by ¼ " is of the order of 15 ps (with ¼ 15

cm and "r ¼ 11:9). The capacitive behavior of the substrate outside the active area is negligible for frequencies below onetenth of 1= . If the capacitance to the substrate, which is introduced by the depletion regions of well diffusions and interconnects overlying field oxide, can be accurately modeled with lumped-element circuits outside the mesh located near the chip surface, the substrate can be modeled as a purely resistive mesh. If the substrate is multilayered, then the network may not be approximated by a resistive network even at lower frequencies [5]. Note that in circuit simulators, such as SPICE, the junction capacitances of active devices are modeled as lumped capacitances outside the mesh. For modeling the substrate by a resistive grid, box integration or Delaunay tessellation (for greater accuracy in and around the more interesting regions of the substrate) may be used [15]. The 3-D resistive mesh is reduced into an equivalent set of nðn þ 1Þ=2 resistances interconnecting the n ports [7], [48]. In this approach, wells are considered ports which are connected to lumped capacitances outside the mesh. Since the substrate is modeled as a purely resistive mesh, its DC macromodel consists of only the steady-state/DC values of the admittance parameters with the higher order mesh moment being zero. The computational complexity of the DC macromodel is much lower than that of the congruence transform-based method and the resulting macromodel is more compact. 2118 Fig. 11. (a) Ports on a substrate resistively connected to one another. (b) Determining resistive coupling between ports using the BEM [6]. 3) BEM: An alternate approach to solving the simplified Maxwell’s equations is the BEM, which can be used for both parasitic and the substrate extraction [49]. This method is more appealing than the finite-difference method because only the ports that connect the substrate to the devices/contacts/wells are discretized [50]. Therefore, instead of discretizing the whole structure, only the relevant boundary features, which are the 2-D substrate contacts (port areas), are discretized. The resulting matrix to be inverted in the network reduction process is much smaller, albeit fully dense [50]. The extraction can be combined with model reduction to obtain simpler models [51]. Another major advantage of the BEM method is that it is not discretization dependent (unlike FDM) [24]. For example, by discretizing a port into a single panel, i.e., assuming a constant current density across the port, the results are within 10% of the actual answer. By a proper choice of the Green’s function of the BEM, only those parts of the substrate boundary that directly interact with the designed circuit (called Bcontacts[) have to be discretized. A Green’s function is used to determine the point-topoint impedance between each pair of discretized ports as illustrated in Fig. 11. The resulting impedance matrix is then inverted to yield the required substrate admittances [52]. The Green’s function, which is the potential at any point in a medium due to a current injected at any point also in the medium, can be determined for the substrate in a quasi-analytical form. This technique effectively reduces a 3-D problem to a 2-D one. Now, we briefly discuss the Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation formulation of the Green’s function. For the resistive substrate case ð"r ¼ 0Þ, Maxwell’s equation reduces to the well-known Laplace’s equation [24] r2 ¼ 0 (9) where is the electrostatic potential. Applying Green’s theorem to the above equation gives the electrostatic potential at an observation point, r, due to a unit current injected at a source point, r0 , as ðrÞ ¼ Z ¼ Zi Jðr0 ÞGðr; r0 Þd3 r where each entry in the impedance matrix zij is given as where Gðr; r0 Þ is the substrate Green’s function satisfying the boundary conditions of the substrate and Jðr0 Þ is the source current density. As all sources and observation points are at the defined ports on the substrate and these are planar and two dimensional, the previous volume integral reduces to a surface integral ðrÞ ¼ Jðr0 ÞGðr; r0 Þda: (11) S This reduces the 3-D problem into a 2-D problem. In addition, because the Green’s function implicitly takes the substrate boundaries into account, there is no need to explicitly consider them when solving the equation where only the port areas (that actually connect to the substrate) need to be discretized to solve the equation. The substrate Green’s function can be determined analytically using classical mathematical techniques [49], [52]–[55]. The substrate Green’s function Gðx; x0 ; y; y0 Þ, with ðx; yÞ and ðx0 ; y0 Þ as the coordinate locations of the observation and source points on the substrate surface, may be expressed as Gðx; x0 ; y; y0 Þ ¼ M X N X fmn cos m¼0 n¼0 mx a    0 mx0 ny ny  cos sin sin b a b (12) where fmn for a homogeneously doped substrate is given by fmn Cmn tanh ¼ ab (14) (10) V Z Here, Cmn is a constant,  is the substrate conductivity, and ða; b; cÞ are the ðX; Y; ZÞ substrate dimensions. For a multilayered substrate profile (of uniform sheet resistivities) a more complicated expression is obtained for fmn . Once the Green’s function is determined, (11) remains to be solved [24]. The solution is obtained using a suitable discretization technique which discretizes each port on the substrate into a set of panels. A system of equations can then be formulated that relate the currents and potentials at all panels in the system. In a matrix form, this is represented as rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! m2 2 n2 2 þ 2 c : a2 b (13) zij ¼ Z Z Si Jðr0 ÞGðr; r0 Þda0 da: (15) Sj In this equation, Si and Sj are the surface areas of panels i and j, respectively. The impedance given by (15) can be analytically determined for rectangular panels once the Green’s function is derived. The matrix Z is then inverted to obtain the substrate admittance matrix Y. We can determine the substrate resistance between any two ports as the reciprocal of the sum of corresponding admittance matrix entries. From a computational point of view, the direct evaluation of the quasi-analytical Green’s function given involves several million floating point multiplications and additions. As this computation must be repeated for every pair of panels, the formulation of the impedance matrix becomes an expensive task for large problems [52]. As an alternative technique, after discretizing the entire substrate surface into a uniform grid of panels, a 2-D discrete cosine transformation (DCT) can be utilized to precompute all the panel-to-panel impedances on the substrate using only OðNlogNÞ operations [54]. Another problem with the BEM approach, in general, is that the inversion of the dense n  n matrix is a cumbersome task. Direct LU factorization requires Oðn3 Þ operations, which is clearly infeasible for a reasonably large problem. 4) Fast Solution of BEM Matrices: To improve the efficiency of the BEM method, multilevel (multigrid) methods, which are efficient iterative techniques, have been developed for first-kind integral equations defined over complicated geometries [51]. In the method, a multigrid iterative solver that includes sparsification algorithms specially tuned to accurately account for the substrate edge effect allows for almost an order of magnitude improvement in the speed of the BEM solution process. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2119 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Alternatively, a fast Eigen decomposition technique may be used that accelerates the operator application in the BEM method and avoids the dense matrix storage while taking all of the substrate boundary effects into account explicitly [50]. For an efficient extraction of the substrate coupling model in a BEM formulation, an Eigen decomposition-based technique in a Krylov subspace solver is used. The model can be incorporated into a circuit simulator such as SPICE to perform a coupled circuit-substrate simulation. To speed up the model computation process at the cost of a slight decrease in accuracy, the use of a precorrected-DCT (PcDCT) algorithm has also been proposed [56]. The main idea is that the effect of an injected current in a panel on the potential of another far away panel can be considered equal for small variations in the distance between panels. The results of an experiment on a heavily doped bulk substrate indicate a speed up of around 180 times compared to the basic Green’s function method with better accuracy and 12 times faster than the Eigen decomposition method. The memory requirements for the PcDCT algorithm are considerably smaller (20 times) than those of the basic Green’s function method. Some savings in memory (three times) is also obtained with respect to the unaccelerated Eigen decomposition algorithm. Several other problems plague BEM-based substrate modeling and simulation [57]. First, the density of the extracted coupling matrix makes later circuit simulation prohibitively costly, because the now-dense circuit matrix must be factored hundreds or thousands of times in each simulation. Second, most methods of obtaining the n columns of the coupling matrix require n matrix solutions, which is computationally costly, making it impractical to solve problems with n larger than a few hundred. To address these problems, a multiscale waveletlike basis for fast integral equation solutions has been proposed [57]. The wavelet basis efficiently represents coarse grain information of the IC geometries. Using such a basis, many entries become small and are neglected with only a small loss of accuracy. The wavelet basis has a multiresolution property; it is shown that reducing the number of nonzero elements by 90% leads to only a 1% reduction in accuracy. The results presented show that for a problem with a few thousand contacts, the method is about ten times faster at constructing the matrix. Other research dealing with the efficient use of BEM and Green’s functions for substrate model extraction is described elsewhere [58]–[62]. Another effort [63] focused on efficiently solving the 3-D mesh obtained for modeling the substrate coupling; a stochastic method for substrate modeling is proposed in [64]. A general modeling of distributed electromagnetic coupling effects including magnetic coupling of adjacent interconnects and/or planar spiral inductors, substrate coupling due to stray electric currents in a conductive substrate, and full-wave electromagnetic radiation is presented in [65]. Also, several macromodels of the substrate between two contacts as a 2120 function of different parameters such as distance, substrate type, and substrate doping have been presented [66]–[68]. 5) Chip-Level Substrate Network Extraction: One simulation tool performs a mixed-signal noise simulation without the presence of devices (using equivalent noise sources) in order to compute the time- or frequency-domain substrate noise waveforms at the bulk nodes of interest; it can be used to analyze chips with more than 1 million devices [69]. After the substrate noise waveforms are computed, a circuit simulation with devices and attached noise sources is performed to assess the impact of noise on the subcircuits of interest. A typical flow for substrate noise analysis verification using the tool is shown in Fig. 12. To efficiently model and analyze the substrate for large designs, an adaptive substrate modeling approach is used. This is achieved through the use of sensitivity analysis to determine which areas of the chip need high model accuracy and where the model accuracy can be relaxed without impacting the accuracy of the overall analysis. Noise sensitivity analysis is also used to measure the impact on substrate noise of a change in a given parameter. By calculating the sensitivity to various layouts and process and package parameters, appropriate measures to minimize substrate noise are determined. C. Chip-Level Mixed-Signal Substrate Coupling Analysis Once an accurate substrate model has been extracted, the location and magnitude of the noise injectors is determined to facilitate the simulation of substrate noise waveforms. The locations of the noise injectors can be determined from the layout and schematic netlist information. To determine the magnitudes and phases of the injected currents, some form of simulation input under assumed switching activity is required. Once this has been ascertained, the problem is reduced to solving a very large RC network with active current sources (Fig. 13). The number of the current sources can be extremely large; e.g., a million transistor mixed-signal design may require a million current sources. To see how a large RC network driven by active current sources is analyzed, suppose that the voltage response at a bulk node of interest vb is desired. The voltage response can be written as vb ðsÞ ¼ z1 ðsÞ:i1 ðsÞ þ z2 ðsÞ:i2 ðsÞ þ z3 ðsÞ:i3 ðsÞ þ . . . (16) where i1 ; i2 ; i3 ; . . . are the current sources at various locations on the substrate, and z1 ; z2 ; z3 ; . . . are their corresponding impedances to the bulk node of interest. The current source values can be determined from a simulation of the original circuit (without parasitics) by observing the currents flowing in the power/ground nodes and device bulk terminals. This can be accomplished either with a Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 12. Verification flow for full chip-level substrate noise analysis [6], [9]. transistor-level circuit simulator or a gate-level eventdriven simulator in conjunction with precharacterized cell libraries as discussed in Section III-A. The currents can be either time-domain waveforms or a composition of spectral values at every frequency ðs ¼ j!Þ of interest. The impedances can be obtained by inverting the admittance matrix formed by the RC substrate network and package inductances (Fig. 13), and the frequency-domain response of vb can be obtained by solving (16) at every frequency of interest. Applying the inverse Laplace transform to this response results in the corresponding time-domain waveform. One advantage of using (16) to calculate the noise response at a bulk node of interest is that each individual noise contributor can be calculated independently. Hence, from (16), the noise contribution at the bulk node of interest from injector 1 is z1 ðsÞi1 ðsÞ. Similarly, z2 ðsÞi2 ðsÞ is the contribution from injector 2, and so on. Thus, the most significant noise contributors can be identified and appropriate measures can be taken to minimize their impact. 1) Macroscopic Substrate Noise Analysis Using High Level Simulation: A macroscopic substrate noise model that expresses the coupling noise as a function of logic state transition frequencies among digital blocks has been proposed [16], [70]. The coupled noise is defined as one of the state variables in a behavioral description of the victims such as analog circuits. Typically, the noise can be expressed by the superposition of voltage changes arising from the digital state transitions in unit time. Thus, it is a function of the state transition frequencies in the digital block that can be easily extracted from a digital logic simulation. This results in the introduction of behavioral noise modeling using a hardware description language (HDL)-based system-level design [70], [71]. A simulation system based on the model was implemented in a mixedsignal simulation environment (Fig. 14) where the performance degradation of a second-order delta-sigma A/D converter coupled to digital noise sources was simulated. The computation of the noise proceeded according to a noise waveform function Fðf eff ; TÞ in parallel with a transient analysis of the mixed-signal circuit under design. The calculated noise was injected into the analog circuit. In noise waveform function, f eff ðnÞ, which is the effective transition frequency, a global state transition count per unit time of T at the nth sampling interval is expressed as feff ðnÞ ¼ m  1X W þ N þ þ Wi
Ni
T i¼1 i i (17) where Ni ðnÞ is the local state transition count of the ith digital subblock and Wi , which is the weight coefficient corresponding to a substrate coupling intensity of the subblock to the sensitive analog circuit, is a relative quantity among the digital subblocks. Superscripts Bþ[ and B
[ Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2121 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 13. Simulation model for full-chip substrate with large number of noise injectors [6], [9]. represent the rising and falling transitions, respectively, T is the noise sampling period introduced to discretize the noise generation process, and Fnclk ð¼ 1=TÞ is synchronous to the system clock ðFsclk Þ. Fðf eff ; TÞ must be continuous and reflect the nature of its transient behavior. In the study, for calculating Fðf eff ; TÞ, a successive function system of f n ðtÞg was adopted. The expression for the system is n ðtÞ ¼ þ n
1 ðTÞ    t feff ðnÞ
feff ðn
1Þ 1
exp
  (18) where n ðtÞ is defined in the interval ½0; T of the nth sampling period, and and  are the model parameters. Fig. 14. Proposed macroscopic substrate noise model [16]. 2122 A shortcoming of this technique is that the coefficients are functions of technology such as circuit and layout details; therefore, the circuit simulator must be run each time any of these parameters is changed. The weighting coefficient Wi models the attenuation of the noise amplitude by distance and guard banding and the ratio of the noise amplitude for rising to falling transitions. To determine the coefficients, evaluation of the substrate noise transmission by circuit simulation is required; one of the modeling methods for substrate equivalent circuits explained in Section III-B should be used. In addition, and  are parameters that determine the amplitudes and widths of the generated noise waveforms, respectively. These are dominated by the substrate structure and thus should be evaluated from experimental results from dedicated test chips consisting of simple noise sources (e.g., inverter arrays, etc.) and wide bandwidth substrate noise sensors. The macromodeling approach is appreciated for capturing the sensitivity and measuring the response of mixed-signal circuits to coupling noise in terms of performance metrics such as SNR and bit-error rate (BER), for which a designer cannot apply SPICE circuit-level simulations. For instance, the observed degradation of total harmonic distortion (THD) shown in Fig. 15 agrees with the reported experiments [26] that were described in Section II-E. Therefore, the model successfully expresses the interaction of the delta-sigma modulation loop dynamics with transient voltage noise injected into the analog signal paths mainly through integrators. Other high-level simulation modeling approaches for substrate Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation days of computation to simulate the 20 periods that are required for the modulator to reach a steady state. Using the periodic analysis approach, a macromodel of the modulator (982 devices, 438 nodes, and 1445 equations) was obtained in less than 1 h of CPU time. Another hour was required to simulate the transient noise coupling from the reference generator. Fig. 15. Simulated in-band power spectrum of second-order delta sigma modulator coupled to substrate noise generator [16]. coupling noise and some experimental verification of the models has been reported [72]–[78]. 2) Periodic Analysis of Mixed-Signal Noise in RF Circuits: For RF circuits, specialized simulation techniques for the analysis of periodic circuits can be used to quickly calculate the response to mixed-signal noise [6]. Following a periodic steady-state operating point analysis, a transfer function analysis computes the transfer functions to the RF circuit output at a single frequency from every noise source in the circuit at every input frequency (i.e., output frequency and all frequencies offset from it by a harmonic of the periodic signal). Using this approach, it is possible to compute the transfer functions from the bulk node of every device in the circuit to a specific output at a given frequency of interest; this results in a set of transfer functions for each bulk node. Once the transfer functions are computed, the circuit no longer needs to be represented at the transistor level. A transient simulation can be performed on digital (and analog) circuits to obtain the transient substrate noise signals. A postprocessing of the signal (Fourier transform) determines the equivalent noise spectra at the device bulk nodes. These noise frequency components multiplied by the transfer functions obtained previously determine the coupling of substrate noise to the RF circuit outputs. To calculate the periodic transfer functions, efficient matrix-free iterative methods for the periodic analysis of RF circuits are used [79]–[81]. The methodology is applied to the verification of the transmit section of a portable radio front-end IC [6]. The measured results on the fabricated IC indicate an RF spur at the output of an up-conversion mixer in the transmit section that was adequately predicted after analyzing the circuit using this method. With roughly 1900 devices, 717 nodes, and 3234 equations to solve, a transient analysis of the modulator and reference frequency generator requires two 3) Application to Automated Placement and Power Distribution Synthesis: The simulation of mixed-signal switching noise has been integrated into several automatic layout tools including a synthesis program that automates the design of the power distribution network [7], [82] and a substrate-aware placement tool [83]. In [7] and [82], the topology of the power grid, the sizing of individual segments, and the choice of I/O pad number and location are simultaneously optimized. The optimization employs combinational optimization techniques and is performed under tight dc, ac, and transient electrical constraints arising from the interaction of the power grid with the rest of the ICVnotably via substrate coupling. Coupling effects are included in the cost function of a simulated annealing-based power distribution synthesis system. In this work, linear macromodels for the digital switching logic circuits are created and the capacitive and resistive coupling to the power rails is modeled as shown in Fig. 16. Each logic circuit is replaced by a linear macromodel. To design a power grid, the tool begins with an initial Bstate[ for the power bus geometry and power I/O pad configuration and then this geometry is perturbed to create a new candidate power grid or pad configuration and update the electrical models for the buses and I/O pads. In the next step, these models are combined with designersupplied circuit macromodels for blocks being supplied by the power grid and for the substrate. With this complete electrical modelVpower grid, blocks, pads, and substrateVthe resulting electrical performance is evaluated and compared against the designer constraints. For example, one might evaluate the coupled noise waveform Fig. 16. Simple linear macromodel of logic block for switching noise [82]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2123 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation at a sensitive node against a designer-supplied peak-topeak noise amplitude constraint. Finally, the optimizer accepts or rejects the perturbation based on the result. The iterative improvement loop is continued until the optimizer determines no further improvement is possible. The main objective is to ensure that the power distribution as a whole (busses, power I/O cell assignment, internal cell decoupling) is designed to meet the dc voltage drop and current density constraints while keeping the transient noise voltage below the user-specified targets. In a substrate-aware mixed-signal placement tool, a set of algorithms for handling the substrate-coupled switching noise in an iterative placement framework is implemented [83]. Traditionally, area and the wire length were the most important concerns. Now, other factors that deal with the interaction between analog and digital sections through the common substrate add a new dimension to this problem. The focus of the tool is on physical design, in particular chip-level macrocell placement, and the approach incorporates a simple switching noise estimate into a simulated annealing placement algorithm. A coarse resistive grid method analyzing the coupling of digital switching noise into the analog macros on the chip is used as shown in Fig. 17. The tool includes models for the chip substrate, noise sources, and receivers on the macrocells. In addition, mitigation measures such as guard rings are incorporated in the inner loop of the placer by low impedance ties from the substrate to the reference potential. The accuracy available in conventional substrate analysis design tools is not needed and is not affordable within a placement framework because such a tool must visit thousands of candidate placement solutions. A number of other research works related to substrate-aware floor planning and placement have been reported [84]–[88]. I V. AVOIDING MIXED-SIGNAL NOISE COUPLING Mixed-signal noise reduction is achieved through various approaches including grounding, shielding, suitable timing of logic, signal routing, and power distribution. These techniques may be broadly classified as: 1) those that attempt to reduce the strength of the Bnoise,[ i.e., the crosstalk source; 2) those that try to minimize the susceptibility of the sensitive circuits to substrate and other types of noise; and 3) those that attempt to minimize the coupling of noise from its source to other areas on the chip [8], [23]. In general, these techniques can be applied through process, circuit design, layout design, and pin assignments. The first and second techniques often require fundamental adjustments in circuit design methodologies, while the latter has the advantage that it places virtually no constraints on the designer and may even be applied to cases involving existing circuits [23]. Generally, signal coupling may not be prevented, but the use of good design practices/strategies/techniques leads to its reduction [18]. A. Reducing Noise Source Strength The main source of undesired signals is digital switching noise. In the following, methods to reduce it are discussed. 1) Circuit Techniques: In purely digital applications, CMOS static logic offers several attractive features such as small static power dissipation, high packing density, Fig. 17. Substrate resistive macromodel [113]. 2124 Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation wide noise margins, and fairly high operating frequencies. The noise generated in CMOS digital circuits, however, is problematic due to the rail-to-rail switching characteristics. In order to avoid or suppress noise generated by logic circuits (the noise source), fundamental adjustments in circuit design methodologies for CMOS are required. First, to prevent unnecessary switching currents, logic/drivers not in use should be shut down. Second, rail-to-rail switching logic families, such as static CMOS, that require large transient currents and therefore generate more switching noise should be avoided; instead, current mode logic (CML), for example, should be considered. Currentmode logic techniques have been developed for highprecision, high-speed, mixed-mode ASIC applications. CML logic families include emitter coupled logic (ECL), folded source-coupled logic (FSCL) [89], [90], and enhancement source-coupled logic (ESCL) [91]; they make use of balanced current steering topologies and therefore create less switching noise. For example, differential ESCL offers low switching noise compared to conventional CMOS logic. This is achieved by steering a constant current to perform the logic operation with a smaller logic swing ðV ¼ V L G 0:2 V dd Þ than static CMOS ðV ¼ V dd Þ. ESCL reduces the power supply digital switching noise current spikes by about two orders of magnitude (e.g., 20– 30
A/gate) compared to static CMOS (e.g., 0.5–1 mA/ gate). The obvious disadvantages of current steering logic families are their nonzero static power dissipation and larger area requirements [92]. 2) Reduction of Simultaneous Switching Noise: Static CMOS digital circuit blocks have high noise margins and are normally not affected by digital switching noise. Hence, in pure digital systems, substrate current is not a problem so long as latch-up does not occur [32]. Only in the cases where the output drivers switch simultaneously is the generated noise sufficiently strong to disturb the operation of gates that are connected to the same V dd =GND grids. This phenomenon is called simultaneous switching noise (SSN). Some problems encountered in digital circuits due to SSN are false triggering, double clocking, and/or missing clock pulses [93]. To reduce SSN, clever circuit design techniques to control di=dt through device, package, and V dd =Gnd grids are needed. Two different methods for custom output driver design are often practiced in application-specific ICs: the current-controlled (CC) and controlled slew rate (CSR) output drivers. The first approach has limitations in speed (G 30 MHz); whereas, the second is a better for higher speeds [93]. Using the second technique, an improvement is obtained in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional drivers and the speed and sink/ source capabilities are preserved. The SSN reduction is achieved requiring only an increase in the silicon area of the output driver. The CSR output driver uses distributed and weighted switching driver segments to control the slew rate of the output driver for a given load capacitance. Using an additional damping resistor in the output driver circuit reduces the power supply/Gnd noise. Another proposed circuit design technique to reduce SSN, tank CMOS (TCMOS), uses the conventional CMOS family with small static power consumption. In this approach, power is provided to the digital circuits through a controlled current injector stage which has the ability to isolate the main power supply bus from the noisy power lines of the digital circuits [92]. To achieve this goal, a tank capacitor is used to store enough energy to power the digital circuits. To reduce the voltage drop along the power supply lines and thus control SSN, the inductance and resistance of the interconnect layers, pads, bonding wires, and package pins should be minimized. For example, if there are different interconnect layers available, lower resistivity layers can be used to minimize resistance and shielding lines can be used to minimize inductance wherever possible. Because the switching currents are proportional to the load capacitances being charged or discharged, circuits with large load capacitances create higher noise on the power supply/Gnd grids. The capacitance should be minimized to minimize the displacement current. In addition, large drivers should be placed as close as possible to the power returns to minimize the parasitic inductance and resistance [18]. The charging/discharging currents, in addition to passing through the chip power rails, are injected into the substrate. To minimize this effect, balanced current steering drivers should be used (and if possible, other circuits) so that the complementary injected currents cancel in the substrate. Another technique to control di=dt is to ramp the clock as slowly as possible (increase its rise time) to prevent excessive switching currents from flowing to the substrate and supply lines. This is especially important for I/O drivers that charge and discharge large capacitors; hence, for these circuits, the rise time should be as slow as possible to meet the system requirements. In addition, a clock skew technique for reducing ground bounce is available [94], [95]. To reduce the dynamic transient current drawn from the supply pins in this approach, the synchronous clock is subdivided into multiple subclocks with relative skews, which distributes the computation across the entire clock period instead of just at its beginning. This is achieved by minimizing the difference between the current peaks and valleys such that the current profile of the entire circuit is relatively smooth. Buffered outputs are also skewed to prevent them from switching simultaneously [24]. Reducing the power-supply voltage is also an effective technique. Reduced voltage swing circuits should be used, especially for I/O drivers, to minimize the switching currents [5], [18]. In a digital signal processing LSI, the noise current was reduced by 20 dB when the digital supply voltage was lowered from 5 to 1.2 V [8]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2125 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation 3) RLC Decoupling Technique and On-Chip Power Supply Bypassing: A key requirement for the integration of analog circuits is a stable analog power supply. Usually, in electronic cards, off-chip capacitors (between Gnd and V dd ) are used to minimize the fluctuations of the power supply voltage. These capacitors act as short circuits for high frequency components of the noise to reduce fluctuations due to switching noise current spikes. For the same reason, on-chip decoupling capacitors are also inserted into digital supply networks. It is, however, necessary to make sure that the power-supply bypassing circuitry does not form a resonant circuit with the bonding wires. One of the ways to prevent this is to utilize large distributed on-chip decoupling capacitances with high self-resonance frequencies. Another method is to include small resistors in series with the bypass capacitors in the power path [96]. In [97], an RLC decoupling method that features an enhanced transient response suited for lowpower low-voltage applications is introduced. It features the resistor in a new LC branch and not in the power path. B. Reducing Noise Susceptibility of Sensitive Circuits There are techniques that attempt to eliminate or compensate the influence of noise on a sensitive analog circuit (the noise receiver). Several design guidelines are described in this section. 1) Analog Circuit Techniques: The differential or balanced circuit technique is used as a countermeasure to common-mode noise, i.e., a coupled common-mode signal is rejected by the circuit itself. Differential circuit topologies also maximize the power supply rejection ratio (PSRR) which is important in minimizing the effects of power-supply/Gnd digital switching noise. From a noise point of view, most analog circuits on a mixed-signal chip should be designed using differential topologies. In addition, the differential circuit layouts should be symmetric so that the coupled noise is completely common-mode between differential device pairs [5]. This may require a custom layout. Although the noise power in a fully differential circuit increases by 1.414, additional device noise is easier to manage from a design standpoint than substrate noise coupling [98]. Since the noise is coupled from the aggressor to the victim based on an impedance ratio, the lower the internal impedance of the sensitive node, the less the coupled noise; hence, the impedance of a sensitive node should be minimized. Another good design practice is to minimize the impedance from quiet buses to the card Gnd=Vdd lines and high impedance analog lines should be shielded and kept far away from noisy digital lines [98]. Another good practice is to limit the signal and the circuit bandwidths to reduce the power of the undesired signals. 2) Mixed-Signal/RF Design Techniques: A digital correction technique useful for the elimination of A/D conver2126 sion error due to noise is used in subranging CMOS A/D converters; power supply line noise is eliminated and the effective PSRR is improved by 25 dB [99]. A monitor comparator array, embedded in the chip, detects the noise and provides error correction data for the A/D outputs. This correction technique is also applicable for the compensation of substrate noise in A/D converters. It is also effective to sample analog signals at times removed from synchronous digital switching events by employing dedicated analog clock phases [24]. The intentional skewing of digital output signals described in Section IV-A2 also reduces the noise floor in the output spectrum of the converter. The techniques described are used in the development of SoC solutions. For example, a single-chip global positioning system (GPS) receiver employs substrate coupling analysis in its mixed-signal/RF implementation flow [1]. Guard bands are carefully placed to mitigate substrate coupling between the 500 K-gate digital baseband blocks and the LNA, which is the most sensitive RF building block in the receiver front end. Dedicated ground pads are assigned to the guard bands that are formed by pþ diffusions on a lightly doped p-type substrate. In addition, block-level placements are constrained by substrate coupling considerations. Consequently, the most sensitive mixer and LNA circuits are located at the die corner and surrounded by IF differential analog circuits such as filters that are next to the digital block, i.e., they serve as a buffer between the noisy digital block and the sensitive RF circuits. Spectrum analysis was also a key factor in the design. The digital clock harmonics are positioned out-ofband far from the weak incoming GPS 1.575 GHz carrier signal. The final single-chip 2.3  2.0-mm design achieves a sensitivity of
152 dBm. It is embedded in a 6.3  6.3-mm SoC that is primarily populated by processor and memory macros. C. Reducing Noise Coupling Propagation Noise reduction is achieved by limiting noise transmission through the common substrate and supply/return routes (the noise paths) using process and layout techniques that include grounding, shielding, and decoupling. In addition, close attention should be paid to signal routing, power distribution, and pin assignments; three important design practices are using separate power supply/ Gnd grids, physically separating the victim and aggressor blocks, and including guard bands in the layout. 1) Placement Considerations Pertinent to Substrate Structure: Clocks should be shielded from the substrate and from sensitive analog circuitry. Additionally, routing differential clocks close together minimizes signal coupling to the substrate or through the air [32]. The power network should be routed using multilevel gridded buses to minimize the line impedance [5]. Another good method of reducing the parasitic inductance of the power grid is to Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation maximize the number of chip power pads/pins. Because the worst inductive near-field coupling occurs at the package leads, the input/output pin assignments should be made carefully. For example, the closer the lead is to the ground lead, the lower is its parasitic inductance. To reduce the coupling from the logic (noisy) circuits to the sensitive analog (quiet) circuits on a high resistivity substrate, one should physically separate the chip/package power supply lines of the noisy and quiet circuits wherever possible. Therefore, the analog and digital regions should have their own isolated power supply connections and respective substrate ties [100]. Where this is not possible, a custom STAR power routing scheme should be employed [18]. In this scheme, one can minimize the length that the power bus is common between the noisy and quiet circuit blocks. Similarly, to prevent any undesired coupling, the signal wires (interconnect layers) of different parts of the chip should be separated as much as possible. The analog ground line should be routed directly from the pad to operational amplifier inputs, for example, and shielded with underlying diffusion. In addition, groups of OpAmps should have their own local current bias [98]. The substrate doping and distance between two blocks determine the path impedance between them ZAB . The signal coupling from block A to block B is a function of this impedance which should be maximized to minimize coupling; this is achieved by decreasing the doping and/ or increasing the distance. Typically, noise coupling via the substrate is less severe in a lightly doped ðp
Þ substrate compared to a heavily doped ðpþ Þ substrate when the (grounded) backside contact is not used. In p
substrates, current flow is more uniform within the substrate because there is no low-resistance bulk. Fig. 18 shows device simulation results for the dependence of peak-to-peak noise on the distance d between a current source transistor and an equivalent drain diffusion; the noise voltage decreases almost linearly with separation [11]. The noise effects in these substrates are highly layout dependent. In addition, the isolation is a weak function of the back-plane inductance [101]. On the other hand, the heavily doped substrate, which is more expensive, has a p
=pþ structure to prevent latch-up. For these substrates, simulation results show that most of the lateral current from the digital noise source to the substrate contacts flows in the heavily doped bulk [11]. Because of the low resistivity and large thickness of the bulk, the pþ part of the substrate shows small path impedance; hence, the injected noise current flows almost directly down through the epitaxial layer into the bulk and then up through the epitaxial layer to the substrate contacts. The heavily doped bulk acts electrically almost as a single node and any switching transient that excites the bulk will affect the entire chip. The isolation in this type of substrate is almost independent of the separation between the contacts beyond a certain critical separation, which depends on the backplane impedance as has been shown via measurement and Fig. 18. Device simulation results for peak-to-peak noise as a function of distance between digital noise source and current source [11]. simulation (Fig. 18) [11], [101]. In a computer simulation, with backplane impedance varying from tens of ohms (bond-wire contact) to several kilo-ohms (epoxy backplane contact), the critical separation was found to vary from 2.5 to 5 times the epi-layer thickness [101]. In experimental work [11], the results showed that the resistance between two substrate contacts was constant for distances more than four times the effective thickness of the epitaxial layer. This suggests that in these types of substrates, increasing the distance between the source and receiver of the undesired signal is not an effective approach for reducing substrate noise coupling. Another noteworthy point regarding heavily doped bulk substrates is that they provide excellent differential-mode substrateisolation compared to p
substrates due to the vertical nature of current flow in these substrates [101]. 2) Guard Ring and Isolation Structures: To stop noise transmission from digital to analog circuits, one can utilize pþ diffusion rings (for p
substrates) that completely enclose a given region as shown in Fig. 19(a). This simple technique is an ohmic guarding structure providing a lowimpedance contact from the supply to the substrate. It is one of the most commonly used isolation schemes and seems to be best suited for preventing crosstalk at high operating frequencies [23]. The ring can be around the sensitive circuit and/or the noisy device. Similar to a substrate contact, we connect the guarding structure to either a supply voltage (ground potential for p
substrates) or a dedicated low-noise analog supply pin [83]. By connecting the guard ring to a voltage, we attempt to fix the voltage of the substrate around the device (circuit) by absorbing the substrate potential fluctuations. The guard ring serves as a low impedance path (typically, the series combination of the diffusion and the wiring) to a quiet potential, thereby flattening the noise profile by Bintercepting[ the substrate Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2127 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 19. (a) Guard-ring diffusion for reducing substrate coupling [23]. (b) Guard-ring diffusion supplemented by placing annular n-type regions around peripheries [23]. (c) Dielectric trench oxide around pþ guard rings. Normally, trenches are lined with a dielectric and filled with polysilicon [23]. (d) SOI CMOS devices dielectrically isolated from one another [8], [104]. (e) Twin-well structure wherein analog and digital CMOS circuits are each formed inside deep p-well regions that are separated by n-type substrate regions [8]. noise before it reaches the protected area. It can reduce the switching noise by almost an order of magnitude by acting as a current sink that keeps the substrate quiet in the immediate vicinity of the sensitive circuit [11]. This success originates from the fact that a significant amount of the substrate current flows near the die surface because of the pþ channel-stop implant. Often these guard rings are supplemented by placing annular n-type regions around their peripheries as shown in Fig. 19(b). The n-well guard diffusion acts to isolate the sensitive analog circuit by interrupting the low resistance channelstop implant and forcing the substrate current to flow through the high resistance bulk. Another type of isolation is guard-band diffusion which is similar to a guard ring. When guard rings are used for isolation, increasing the spacing between the source and sensor is not an efficient scheme for reducing crosstalk [23]. In heavily doped bulk substrates, the pþ layer is referred to as the backplate and if the backside of the substrate has an ohmic contact, the contact is called the backside gate [18]. Because the pþ bulk behaves electri2128 cally as a single node, the attenuation of the voltage fluctuations in the bulk through the use of a low-impedance connection to a quiet negative supply voltage should reduce the substrate crosstalk. If a (grounded) backside contact is used, the undesired signal injected into the substrate is absorbed by the backside contact which fixes the substrate voltage to ground and makes the coupled signal to the substrate invisible to other circuits. It should be noted that grounding the back of the wafer introduces additional packaging complexities and increases the cost [23]. In addition, recent experimental results [13] show that the presence of a grounded backside contact has negligible influence even in a heavily doped wafer if the noise is propagated via the power lines when a quiet supply line is not used [18]. For p
substrates, due to the high resistance of the substrate, the (grounded) backside contact is not of much use because it cannot set the substrate potential everywhere to ground. In general, guard structures are not found effective in improving the isolation in p
=pþ substrates due to the vertical current flow [11], [101]. Simulations [11] indicate Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation that an n-well guard diffusion, which breaks the pþ channel stop implant, has almost no effect because most of the substrate current flows in the heavily doped bulk and not in the channel-stop diffusion near the die surface. On the other hand, the simulations show that n-well guard rings are effective when most of the induced substrate current flows through the pþ field implant region close to the wafer surface of p
substrates [23]. In this case, the n-well breaks the low resistance path for the substrate noise current by forming a reverse-biased p–n junction and provides better isolation by forcing the current to flow through the more resistive p
substrate. In another study [101], narrow guard rings are found to be preferable to wide guard rings. The isolation provided by the guard rings was a weak function of the width of the ring. However, the noise that is sensed by the guard ring and injected into the substrate increases rapidly with increases in the guard-ring size. A figure-of-merit for the effectiveness of the technique is the equivalent resistance from the substrate to the ground ohmic contact. This resistance is a function of the number of ohmic contacts; therefore, careful arrangement of guard bands with dedicated routes and pads is necessary for an effective use of this technique. Practical guidelines for the placement and biasing of the guard rings appear in [97]. Generally, both guard rings and bands increase the size of the circuit due to the pþ guard structures and increase the price due to the dedicated package pins. Another approach, shown in Fig. 19(c), consists of using a dielectric trench oxide around the pþ guard rings [23]. Normally, trenches are lined with a dielectric and filled with polysilicon. In [102]–[104], an Si SOI process is suggested to reduce crosstalk wherein SOI CMOS devices are dielectrically isolated from one another as shown in Fig. 19(d). We may also use a combination of an SOI structure and trench isolation. Here, the buried oxide layer (SOI) together with a trench whose thickness reaches the buried oxide layer is used to create pockets of Si that are completely dc isolated from each other. A triple-well structure has also been proposed to suppress signal coupling [8]. In this case, analog and digital CMOS circuits are each formed inside deep p-well regions that are separated by an n-type substrate as shown in Fig. 19(e). Further isolation can be achieved by etching a gap between the analog and digital circuits from the backside of the wafer [105]. The experiments show that an interference coupling of 35 dB above the noise floor is completely removed when a gap is etched around the analog circuit. The compatibility with low-cost CMOS technology, however, must be confirmed before it can be adopted for SoC integration [8]. To suppress undesirable substrate coupling, an approach called -technology (particleenhanced isolation) has been proposed [106], [107]. In this technology, energetic proton beams are applied on the already manufactured mixed-mode IC wafers at predetermined locations prior to packaging. In this way, local semi- insulating regions on silicon wafers for device isolation are created which can minimize substrate coupling and realize high Q inductors. Measured results show a reduction of 25–30 dB in coupling and an enhancement of two-to-three times in inductor Q values. The effectiveness of the isolation structures and placements discussed must be carefully considered in the design of SoCs that embed RF circuitry because isolation diminishes at higher frequencies. For instance, surrounding a sensitive device with a deep n-well stripe shows better isolation than covering the whole area by a single deep n-well when gigahertz-range noises exist [108]. The deep n-well breaks up a low-resistive pþ sheet formed by a high-dose channel-stop implant on a p-type substrate surface. The effectiveness is further enhanced by the use of a high resistivity substrate. Finally, the placement of the guard walls that have a wide strap of p
or deep n
-type well between the digital and RF parts has led to the successful implementation of a single-chip Bluetooth transceiver [109] and a WLAN chip [110]. An RF isolation scheme using a through-the-substrate metallized trench for suppressing substrate coupling has also been proposed [111]. 3) Active Noise Reduction Techniques: If the inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise, a technique that utilizes forward-biased nþ p
guard-ring diodes (Fig. 20) is useful [112]. Simulation results show a noise reduction by an order of magnitude in p
=pþ substrates. The diodes were used to generate a relatively large on-chip capacitance that resonates with the substrate lead inductance to form a bandpass filter. In other words, the resonance creates a very low impedance path to ground that suppresses the substrate noise. The frequency of the filter is adjusted by changing the current through the diode and, hence, its capacitance. Fig. 20. Model of coupling through substrate in mixed-mode circuit showing guard-ring diode [112]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2129 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 21. Active guard-band technique [114]. BActive guard-band filtering[ [8], [113], [114] is a circuit technique that controls the noise source using a guard-band structure. Instead of using the ground connection of conventional guard bands, a noise cancellation signal is actively supplied to cancel the digital noise through the guard band as depicted in Fig. 21. A feedback operational amplifier (with a gain of A) can precisely generate the noise cancellation signal Vout based on the actual noise source Vn detected by one guard band on the chip. The noise cancellation signal has an inverse value to the substrate noise. This is done within the amplifier feedback loop, which includes the guard bands and the substrate. The substrate noise transfer ratio ðV=Vn Þ is given by 1=ð2 þ AÞ for the active guard band. Another active noise suppression technique is reported in [115]. V. EXPERIMENTAL VERI FICATION OF MIXED-SIGNAL NOISE COUPLING Many research activities have focused on studying various possible isolation mechanisms for substrate noise reduction and providing designers with evaluations of preventive measures. In these efforts, various techniques have been proposed to accurately measure and/or estimate noise by simulating the characteristics of noise sources, noise paths, and affected circuits in an actual CMOS chip. A. Measurement-Based Approaches The earliest results of on-chip substrate noise measurements were reported in [115] and [116], where a choppertype clocked voltage comparator measured the amount of substrate voltage variation. The comparator was initially auto-zeroed at a fixed reference voltage and it then repeatedly made comparisons against a stepwise input voltage which was in a meta-stable region. Without substrate noise, the comparator shows a very steep transition of the output probability from zero to one. When a digital circuit was embedded in the same chip and ran asynchronously with the comparator, the transition region widened due to the dynamic shift of the auto-zeroed reference point 2130 caused by the change in substrate voltage. The measured quantity was the amount of the substrate voltage variation averaged over the digital clock cycles of interest. Experiments showed a clear correlation between the amount of substrate voltage variation and the number of the activated logic gates. In [117] and [118], the same authors reported other substrate noise waveform measurements using the same detection technique where the comparator and the noise-source digital circuit was clocked synchronously and the phase difference also changed stepwise. Based on the sampling principle, the time series of the center voltage in the meta-stable region approximated the substrate noise waveform. Since the chopper comparator is in an openloop configuration, it has a large gain and bandwidth with which to capture the substrate voltage variations. It is also biased in the meta-stable region when sensing the substrate. The sensitivity to the substrate voltage comes mainly from back-gate transconductance ðgmb Þ of the MOSFETs comprising the comparator. Since the variations are measured indirectly, the linearity and bandwidth of the measurements could not be determined precisely. A direct sampling technique for substrate noise measurement is proposed in [10] where a detector named SF þ LC is used. The detector consisted of a p-channel source-follower (SF) with an input probe located around pþ area on the surface of a p-type substrate and a latch comparator (LC) connected to the source-follower output as shown in Fig. 22. The SF picks up the substrate potential around the probe and the LC discretizes the level-shifted output voltage of the SF through successive comparisons with a stepwise reference voltage provided externally. The sampling occurs at every latch operation. The SF provides good linearity over an input voltage range of the order of 1 V along with a gain of slightly less than unity and a bandwidth of a few gigahertz even when followed by the LC. The authors demonstrated waveformaccurate substrate noise measurements with voltage and time resolutions of 100
V and 100 ps, respectively. It was shown that there was consistency between the substrate noise waveforms acquired by the direct measurements and those obtained by the comparator-based indirect Fig. 22. On-chip noise probing circuit consisting of source-follower (SF) and latched comparator (LC) [10]. Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation measurements [10]. The former can achieve an absolutevoltage quantitative evaluation of the substrate noise, whereas the latter can achieve a relative evaluation. Continuous-time (CT) measurements of substrate noise use analog differential amplifiers where one input is connected to a quiet reference voltage and the other is connected to the substrate of a nominal ground voltage (0 V) through a p-channel source-follower [16] or through capacitive coupling [119]. Although the CT scheme reduces the complexity of measurement setups, the measurement bandwidth is severely limited by the amplifier and is typically less than 1 GHz. In [120], another measurement method to characterize substrate coupling between digital and analog sections of a mixed-signal CMOS chip is proposed where the induced noise and spurious signals were measured by a custom-designed analog sensor setup. B. Chip-Level Noise Measurements The transition controllable noise source (TCNS) shown in Fig. 23 includes a multiphase clock (Ck[0:8]) generator consisting of nine delay elements and a matrix of noise source units (NSU) in the form of nine rows times 12 columns [10]. The number of NSUs activated by each edge of Ck can be set from zero to 12. The delay element has bias voltages Vn and Vp for regulating the rise and fall delays, respectively. In addition, inverse or noninverse transitions among adjacent noise source blocks are selected by the signal BSel.[ The NSU has 30 inverters operating in parallel, where each inverter has a 50-fF load capacitor to the substrate corresponding to the typical parasitic capacitance of two fanouts and local wiring. Minimum gate length is used and widths are chosen for about 200-ps rise and fall transitions when driving the Fig. 23. Transition-controllable noise source (TCNS) circuit [10]. load capacitors. The TCNS can generate substrate noise with controlled transitions in size, inter-stage delay, and direction. Multiple-point measurements on a single substrate were made by arraying the SF þ LC detectors shown in Fig. 24 [19]. A combination of TCNS and arrayed SF þ LC can serve as a reference structure for assessing substrate noise generation and substrate coupling for a given CMOS technology. An example of such a test chip is shown in Fig. 25; it was fabricated in a commercial 0.3-
m 3.3-V CMOS process with p-type bulk substrate [121]. The chip included two TCNS blocks in the top right and bottom left quadrants, a victim PLL circuit in the top left quadrant, and 12 SF þ LC circuits placed along four different axes at the periphery of the noise source and inside the PLL. The substrate noise waveforms shown in Fig. 2 were measured by SF þ LC for TCNS running with the smaller delay among Ck[0:8] ðT s Þ in Fig. 2(a) and with a larger Fig. 24. Arrayed source-follower + latched comparator detectors for multiple-point substrate noise measurements [19]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2131 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 25. Micrograph of testchip with two TCNS circuits and 12 source-follower + latched comparator detectors [121]. delay Fig. 2(b). The shortest delay caused a single large peak noise due to large di=dt coupling to the parasitic inductance, while positive peaks corresponding to each edge of Ck with rising and falling transitions appear for the larger T s . The observed difference in the substrate noise waveform from the identical digital noise circuit also results from the fact that the major cause of the substrate noise is the leakage of the power-supply/ground bounces. The location dependence of the peak-to-peak substrate noise amplitude obtained from the measurements by the arrayed SF þ LC detectors compared to the simulation with a chip-level substrate network extraction is shown in Fig. 26. The distance of each detector from the first one is given on the x axis of each graph. The average absolute error between the simulated and measured re2132 sults is 4.5 dBV. The substrate noise waveforms for an industrial standard processor, Z80, were measured by the SF þ LC detector [44]. A test chip fabricated in a 0.25-
m CMOS technology carried the processor that was implemented through a standard logic-cell based automated place and route design flow. On the other hand, the TSDPC-based macromodeling technique discussed in Section III-A was applied to the Z80 core along with a chip-level substrate network extraction. The substrate noise waveforms from measurement and simulation shown in Fig. 27 indicate that the modeling of the power supply/ ground bounces as a primary source of noise injection is effective enough for practical CMOS digital circuits. In a recent experiment [122], power supply/ground/substrate noise measurements for 90-nm 1.2-V CMOS digital circuits Proceedings of the IEEE | Vol. 94, No. 12, December 2006 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation up to 1 GHz were reported. The study shows the everincreasing importance of considering the substrate coupling issues in the design of state-of-the-art SoC systems. C. Addressing Noise Coupling 1) Verification of Isolation Schemes: There have been some recent experimental studies on the efficiency of isolation schemes. In [123], different substrate isolation techniques in a typical 0.18-
m CMOS process technology, with and without deep n-well (DNW), were studied. The results were presented on the efficiency of the guard ring, the substrate contact size and proximity, and the DNW at various biases. The isolation was measured by js21 j. An nþ to Psub junction diode was used as both the source of the noise injection into the substrate and as the sensor for the noise. It was shown that isolation based on DNW worked well up to several gigahertz, but at higher frequencies, the pþ guard ring and DNW were comparable in reducing substrate coupling. A study on isolation schemes at RF frequencies is reported in [124]. 2) Active Guard-Band Filtering: The effects of substrate noise reduction by the active guard-band filtering technique discussed in Section IV-C have been examined by measurements. In [113], for a 0.8-
m CMOS test chip, it was shown experimentally that substrate noise was suppressed to less than 1% (
40 dB)Vcompared to the ground connection (
3 dB)Vof the original noncanceled noise for frequencies below 8 MHz. The noise suppression effect was also observed at frequencies up to 20 MHz using an external operational amplifier [114]. The influence of (external) parasitic impedance was found to be a key factor in noise suppression. An active guard-band filter with an on-chip noise cancellation circuit is even more effective for noise suppression for high frequencies, because it eliminates the parasitic impedance due to external components. In the continuation of the work in [125], an ac coupling configuration of an active guardband filter supplies a substrate noise cancellation signal to a ground-level substrate using a single 3-V supply for onchip circuits. The performed experiments and simulations show that the noise-suppression effect depends on the guard-band arrangement. Simulation can be used to optimize the arrangement to strongly suppress noise effects. The applicability of the technique has frequency limitations resulting from the limitations of the Opamp. In a similar approach, a negative feedback-based active noise reduction method for mixed-signal design was presented in [126]. By sampling the noise and reinjecting it into the substrate with reversed phase, a negative feedback loop is formed. For the fabricated circuit, the negative feedback technique reduced the substrate noise to 17% of its original level. Fig. 26. Simulated and measured peak-to-peak noise amplitudes at various points [121]. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2133 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Fig. 27. Simulated and measured substrate noise waveforms from Z80 processor [44]. 3) Reduced Noise Digital Design: Applying modifications to the physical design of highly integrated digital circuits for the reduction of the substrate noise can lead to a substantial cost increase. Measurements among various logic techniques clarify the tradeoffs between cost and the amount of noise reduction. The current steering logic described in Section IV-A generates much less substrate noise than the conventional CMOS logic due to the suppression of current spikes flowing to the power supply/ ground grids [127]. However, the logic family needs analog-like design of each gate in terms of the input/output voltage level, fall/rise transition times, and static power consumption. The reduced supply bounce (RSB) CMOS logic proposed in [128] applies separate wirings of circuit ground (connecting to source terminals of NMOSFETs) and substrate ties (connecting to body terminals of NMOSFETs) and inserts a series resistance between the two wirings, as well as between the power supply and n-well ties. Measurements show that the substrate noise from shift registers comprising RSB CMOS logic was approximately constant at less than 10 mV versus the number of circuits. On the other hand, the registers implemented REFERENCES [1] T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase, H. Usukubo, and M. Katakura, BA complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-
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SUMMARY To understand and address the problem of noise coupling in mixed-signal integrated circuits, many research activities have been performed and many more are ongoing. These efforts include modeling methods and computer simulation techniques for mixed-signal noise coupling, common engineering design practices to control the problem, and experimental/simulation studies of the effectiveness of different shielding mechanisms for the noise coupling. These efforts were reviewed in this paper. The physical phenomena responsible for the generation of the undesired signals were described and the media transporting the signal from the source to the destination were described. In addition, different approaches for modeling the source and coupling media and subsequent computer methods to simulate the coupling were described. Finally, techniques to minimize the coupling and experimental verification of these techniques were reviewed. h ACM J. Wireless Networks, vol. 4, pp. 41–53, Jan. 1998. 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Iwata, BPhysical design guides for substrate noise reduction in CMOS digital circuits,[ IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539–549, Mar. 2001. [130] M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. G. E. Gielen, and H. J. De Man, BMethodolgy and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits,[ IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1383–1395, Nov. 2002. ABOUT THE AUTHORS Ali Afzali-Kusha (Senior Member, IEEE) received the B.Sc. degree from Sharif University of Technology, Iran, in 1988, the M.Sc. degree from the University of Pittsburgh, Pittsburgh, PA, in 1991, and the Ph.D. degree from University of Michigan, Ann Arbor, in 1994, all in electrical engineering. From 1994 to 1995, he was a Postdoctoral Fellow at the University of Michigan. In 1995, he joined the University of Tehran where he is currently an Associate Professor in the School of Electrical and Computer Engineering, Director of the Low-Power High Performance Nanosystems Laboratory, and the Head of the Nanoelectronics Center of Excellence. During research leaves from the University of Tehran in 1998 and 1999, he was a Research Fellow at the University of Toronto and the University of Waterloo, respectively. Makoto Nagata (Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Japan, in 2001. From 1994 to 2002, he was a Research Associate at the Research Center for Integrated Systems, Hiroshima University, and also a Research Associate of the Department of Electrical Engineering, Hiroshima University. He is currently an Associate Professor of the Department of Computer and Systems Engineering, Kobe University, Japan. His research interests include design techniques for mixed analog/RF/digital integrated circuits, where topics include powersupply and signal integrity issues, substrate coupling and/or substrate crosstalk analysis and reduction methodologies, mixed-signal test and diagnosis techniques, and development of merged analog-digital signal processing architectures. Dr. Nagata has been a member of the technical program committee of the Symposium on VLSI Circuits since 2002, Asia and South Pacific Design Automation Conference in 2003, 2004, and 2006, and Asian Solid-State Circuits Conference since 2005, and an Associate Editor of the IEICE Transactions on Electronics since 2002. Vol. 94, No. 12, December 2006 | Proceedings of the IEEE 2137 Afzali-Kusha et al.: Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Nishath K. Verghese (Senior Member, IEEE) received the B.S. degree in electrical engineering from Birla Institute of Technology and Science, India, and the M.S and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA. He was Chief Technologist at EDA startup Apres Technologies and a principal at CadMOS Design Technology, where he codeveloped and commercialized noise analysis software tools for digital and mixed-signal integrated circuits. Subsequent to its acquisition by Cadence Design Systems, he served as Engineering Director leading the development of Cadence’s timing and noise analysis products. Currently, he is Vice President of Research and Development at Clear Shape Technologies, an EDA startup developing design for manufacturing software products. He has published multiple patents in the areas of timing analysis, power variation, and crosstalk. He has also coauthored and presented more than 30 conference papers, journal articles, and invited seminars and has written two books on the topics of signal integrity and noise. 2138 David J. Allstot (Fellow, IEEE) received the B.S. degree from the University of Portland, Portland, OR, the M.S. degree from Oregon State University, Corvallis, and the Ph.D. degree from the University of California, Berkeley. He has held several industrial and academic positions and has been the Boeing-Egtvedt Chair Professor of Engineering at the University of Washington, Seattle, since 1999. He is currently the Chair of Electrical Engineering. He has advised approximately 80 M.S. and Ph.D. graduates and published about 225 papers. Dr. Allstot is a member of Eta Kappa Nu and Sigma Xi. He has received several outstanding teaching and advising awards. Other awards include the 1978 IEEE W. R. G. Baker Prize Paper Award, 1995 IEEE Circuits and Systems Society (CAS-S) Darlington Best Paper Award, 1998 IEEE International Solid-State Circuits Conference (ISSCC) Beatrice Winner Award, 1999 IEEE CAS-S Golden Jubilee Medal, 2004 Technical Achievement Award of the IEEE CAS-S, and the 2005 Aristotle Award of the Semiconductor Research Corporation. He was an Associate Editor of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing from 1990 to 1993 and its Editor from 1993 to 1995. He was on the Technical Program Committee, IEEE Custom Integrated Circuits Conference, from 1990 to 1993, Education Award Committee, IEEE CAS-S, from 1990 to 1993, Board of Governors, IEEE CAS-S, from 1992 to 1995, Technical Program Committee, IEEE International Symposium on Low-Power Electronics and Design, from 1994 to 1997, Mac Van Valkenberg Award Committee, IEEE CAS-S, from 1994 to 1996, and Technical Program Committee, IEEE ISSCC, from 1994 to 2004. He was the 1995 Special Sessions Chair, IEEE International Symposium on CAS (ISCAS), an Executive Committee Member and the Short Course Chair, ISSCC, from 1996–2000, Co-Chair, IEEE Solid-State Circuits (SSC) and Technology Committee, from 1996 to 1998, Distinguished Lecturer, IEEE CAS-S, from 2000 to 2001, Distinguished Lecturer, IEEE SSC Society, from 2006 to 2007, and the Co-General Chair, IEEE ISCAS in 2002. Proceedings of the IEEE | Vol. 94, No. 12, December 2006