Double Gate TFET.pdf

Materials Focus Vol. 7, pp. 1–7, 2018 (www.aspbs.com/mat) Copyright © 2018 by American Scientific Publishers All rights reserved. Printed in the United States of America Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon N. Guenifi1, ∗ , S. B. Rahi2 , and T. Ghodbane1 1 2 LEA Electronics Department, University Mostefa Benboulaid of Batna 2, Batna (05000) Algeria Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India ABSTRACT KEYWORDS: Tunnel FET, High- Dielectric, Subthreshold Slope (SS), Band-to-Band Tunneling (BTBT), Quantum Mechanical Transport QMT. 1. INTRODUCTION The inability, to reduce power density with each progressive technology node has been a dominant constraint for modern semiconductor players. Various techniques have been proposed to reduce computational power spanning from the architecture level to the fundamental semiconductor device level are being actively explored. Tunnel Field-effect transistors (TFETs), based on band-to-band tunneling (BTBT), a quantum mechanical transport (QMT) phenomenon has gained a lot of attention in the modern research community due to its potential for reducing power dissipation for advanced integrated circuits (ICs). This ever increasing interest owes to their feasibility to overcome the 60 mV/dec subthreshold slope limitation of the standard MOSFETs,1–4 as well as compatibility.5 TFET is basically a p–i–n structured device. The device operation requires reverse bias to realize tunneling phenomenon between sources and drain regions with a sufficient level of gate voltage.6–12 ∗ Author to whom correspondence should be addressed. Email: guenifi_2000@yahoo.fr Received: xx Xxxx xxxx Accepted: xx Xxxx xxxx Mater. Focus 2018, Vol. 7, No. xx 2169-429X/2018/7/001/007 Recently, many research groups across the world have reported many proposed devices designed to overcome the on-state current limitation in TFET. The double gate TFET (DG-TFET) with high- dielectric is an effective way to improve the on-current (ION , while taking advantage of steeper subthreshold slope and lower OFF-current.12–23 2. ANALYTIC ANALYSIS OF SENSITIVITY For MOSFETs, the analytic expression for current in a subthreshold regime, where most of current modulation as a function of gate voltage occurs, is given approximately by:12   VG IDS = IOFF exp (1) Vth 1 + CS /COX  where Vth equals kT /q and IOFF is the OFF current at VG = 0. CS represents the semiconductor capacitance and it is a function of ch and tch for short-channel devices. In case of TFETs, the approximate equation for the I –V characteristics leads as follows:12     √ ∗ (2) Eg + qVG − Eg IDS = IOFF exp A m doi:10.1166/mat.2018.1600 1 ARTICLE Increased static and dynamic power dissipation in the integrated circuits (ICs) are the main obstacle for growing demands of smart phones and laptops, which require semiconductor devices having low power operation. As the conventional MOSFET has a thermodynamic limit of 60 mV/decade at 300 K on subthreshold slope (SS), so the device based on the mechanism other than diffusion over a thermal barrier came into existence. In this regard, Tunnel-FET (TFET) has emerged as a promising replacement. Due to its lower subthreshold slope (<60 mV/decade at 300 K), reduced OFF-current (IOFF ), reduced power consumption, and negligible short channel effects, TFETs have achieved a lot of attention in the recent years. In the present research work, double-gate TFET (DG-TFET) device has been investigated. The simulation result shows a very good ION /IOFF ratio (1012 ) and low SS (∼41.54 mV/dec). The DG-TFET has very low off current, IOFF (∼10−17 A/m) and ON-current of (ION ) ∼10−5 (A/m) using gate bias in the vicinity of 0.5. In addition, we have optimized the device parameters, thus improving the ION current and the ION /IOFF ratio yield for two kinds of technologies (using HfO2 or SiO2 as gate dielectric). A comparison between the two technologies was made. Gate to drain (Cgd ) capacitance as function of gate to source voltage VGS as well as drain to source voltage VDS at frequency f = 1 MHz, Cgd is weaker using SiO2 as gate dielectric compared to HfO2 . Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon Guenifi et al. where A is the total tunneling distance which is the sum of natural scaling length  and source depletion width WD (A =  + WD , q is the unit charge and Eg and m∗ are bandgap and effective mass of the channel material, respectively. The subthreshold swing of a device is defined as: the change in gate voltage which must be applied in order to create a one decade increase in the output current6 12 S= dVGS mV/dec dlog IDS  ARTICLE That the tunneling probability, T E is given by:12 √    4 2m∗ Eg3/2 si T E ∝ − tox tsi 3eh̄Eg +  ox (3) (4) In Eq. (4), m∗ is the electron effective mass, Eg is band gap, is the energy range over which tunneling can take place, and tox , tsi , ox , si are the oxide and silicon films thickness and dielectric constants respectively, and h̄ is the reduced Planck’s constant. The tunneling window ( ) in the tunneling probability is written as follows:12 = EVch − ECS 3. STRUCTURE AND SIMULATION METHODOLOGY The electrical performance of DG-TFET was investigated using Silvaco TCAD Atlas 2D software V5.15.32 R.10 The double gate provides electrostatic control over the channel in which the drain field line cannot affect or disturb the source-to-channel barrier and it promisingly reduces the short channel effects. The DG-TFET, adopted in the present research work is shown in Figure 1, having three regions: n-type semiconductor bar forming source and channel region, and p-type semiconductor by forming drain region. In between two regions an intrinsic semiconductor layer is sandwich. The quantum mechanical transistor (QMT) has reached such small dimensions for doping concentration gradients are: 7 5 × 1020 cm−3 , 1010 cm−3 and 5 × 1018 cm−3 for the source, intrinsic, and drain regions respectively. Doping has been optimized to create the maximum ON-current (ION , while keeping OFFcurrent (IOFF  low. In order to have a minimal IOFF , the Fig. 1. Structure of double gate TFET (DG-TFET). 2 Fig. 2. Atlas resolution algorithm of double gate TFET. doping of the source is slightly lower compared to that of the drain. The flow chart for present research work is shown in Figure 2. Fig. 3. Tony plot display using 2D mesh of double gate TFET. Mater. Focus, 7, 1–7, 2018 Guenifi et al. Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon Table I. Design parameters considered for simulation. Parameters Values Gate length (Lg ) Drain and source lengths (LD , LS  Oxide thicknees (tox ) Channel thicknees (tsi ) Source concentration (Na ) Intrinsic concentration (Nd ) Drain concentration (Nd  Gate voltage (Vg ) Supply voltage (Vdd  50 nm 100 nm 2 nm 10 nm 7 5 × 1020 cm−3 1010 cm−3 5 × 1018 cm−3 1.0 V 0.5 V Table II. Parameters oxide gate used in simulation. Oxide gate Parameters Bandgap (eV) Relative dielectrics constant SiO2 Si3 N4 ZrO2 HfO2 9 3.9 5.3 7.9 5.7–5.8 22 4.5–6 25 Fig. 4. Energy band-diagram (a) at VGS = 0.0 V (OFF-state) for DG-TFET. Mater. Focus, 7, 1–7, 2018 4. RESULTS AND DISCUSSION Using 2-D numerical device simulator, the electrostatic performance of DG-TFET is analyzed. Figures 4 and 5 show the simulated energy band diagram of DG-TFET, shown in Figure 1. With the help of the energy band diagram the ON–OFF state conduction phenomenon of the DG-TFET is explained. As shown in Figures 4 and 5, when VGS = 0.0 V and VDS = 0.0 V. The device is in OFFstate with very large tunnel barrier width, and therefore the electrons do not have enough energy to move from the valance band of the source to the conduction band of the channel. On application of sufficiently high gate voltage ARTICLE The DG-TFET, as shown in Figure 1, consists of p+ source, intrinsic channel and n+ drain. The local tunneling models were used to calculate tunneling current from the source to drain with varying gate voltage (VGS . The I –V characteristics of DG-TFET have been plotted and investigated by using Newton method to solve numerical system. The choice of the mesh under atlas is a vital step to have a convergence. Figure 3 shows the tony plot display using 2D mesh of DG-TFET. The gate dielectric layer must be sufficiently thin and therefore, we have taken the oxide thickness tox of 2 nm. The work function of the metal work function, M used is 5.2 eV. The drain, source and intrinsic region lengths, LD , LS and LG are taken as: 100 nm, 100 nm and 50 nm respectively. The silicon thickness tSi is 10 nm for DGTFET. All the physical parameters use in work is tabulated in Table I. The electrical parameters of used dielectric materials is shown in Table II.19–21 Fig. 5. Energy band-diagram at VGS > 0.0 V (ON-state) for DG-TFET. Fig. 6. The electric field behavior analysis of DG-TFET. 3 Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon Guenifi et al. been observed that, the tunnel width decreases and there is a shift of the conduction band downwards. Thus, the gradual enhancement of the gate bias degrades the barrier width and causes an increased tunneling of carriers, indicated in Figure 5. Figures 6 and 7 shows the internal electric filed and surface potential inside the device. In both (Figs. 6 and 7), there is relative comparison between ON and OFF-state. Since, HfO2 is the core material in the gate stack in high- metal gate devices for technology nodes less than 45 nm,22 23 therefore we have used it in our device simulations. Figure 8 shows the transfer characteristic of DGTFET. As shown in Figures 9((a) linear (b)) semilog plot), the variation of leakage current (IOFF  is almost constant for all values of VDS . ARTICLE Fig. 7. Potential surface for DG-TFET structure for VGS = 0.0 V and VGS = 1.0 V. (i.e., VGS = 0.5 V and VDS = 1.0 V), the width of tunneling barrier is reduced and the device switches to ON-state. When the device switched from the OFF-state to the ON-state, an increase in the electric field is observed. It has Fig. 8. Plot of the transfer characteristic (IDS –VGS , regarding different gate oxide in Atlas of a DG-TFET device with LG = 50 nm (a) linear (b) plot Semilog plot. 4 Fig. 9. Device transfer characteristics for double gate N-TFET with a variation of VDS (a) plot linear (b) plot Semilog. Mater. Focus, 7, 1–7, 2018 Guenifi et al. Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon Table III. Lists of the computed electrical parameters of the DG-TFET. Oxide gate Parameters ZrO2 HfO2 Si3 N4 SiO2 Vth (V) 0.2 0.2 0.45 0.5 SS 41.59 41.54 43.99 46.89 (mV/decade) 5 26 × 10−5 4 38 × 10−5 5 84 × 10−6 1 118 × 10−6 ION (A/m) IOFF (A/m) 5 02 × 10−17 4 03 × 10−17 2 52 × 10−17 2 43 × 10−17 ION /IOFF 105 × 10+12 109 × 10+12 2318 × 10+11 461 × 10+10 Fig. 10. Capacitance voltage characteristics showing the gate (Cgg ), gate to source (Cgs ), and gate to drain (Cgd ) capacitance as function of gate to source VGS for for DG-TFET extracted at f = 1 MHz. Mater. Focus, 7, 1–7, 2018 Fig. 11. Gate-to-drain capacitance Cgd as a function of gate to source voltage VGS for different drain to source voltage VDS for DGTFET extracted at f = 1 MHz. Figure 10 shows comparison between available capacitance such as: (Cgd , gate-to-source (Cgs  and drain-tosource (Cds . The capacitance voltage (CV) characteristics showing the gate (Cgg ), gate to source (Cgs ), and gate to drain (Cgd ) capacitance as function of gate to source VGS for for DG-TFET. Due to the presence of a source side tunnel barrier, the gate-to source capacitance (Cgs ) is very small. It explains that BTBT has negligible influence in the charge distribution of a DGTFET. While, Cgd (gateto-drain capacitance) reflects the entire gate capacitance (Cgg ). The Cgd decreases and shifts to the right when, the drain voltage (VDS  increases. This is due to the reduction of the tunnel distance as was observed on the energy bands, this observation was ensured by the simulation. Fig. 12. Gate-to-drain capacitance Cgd as a function of drain to source voltage VDS for different gate to source voltage VGS for DG-TFET extracted at f = 1 MHz (SiO2 and HfO2 . 5 ARTICLE It is evident from the results that, the drain current performance is improving with replacement of high- gate materials instead of using conventional SiO2 . Threshold voltage (Vth  of DG-TFET reduces with high- gate, as shown in Table III due to improved electrostatic filed inside tunneling region. This is also a scientific indication for lower power supply. The output characteristic is improved with increasing drain voltage and achieves its optimum value for drain voltage VDS equal to 1.0 V. The use of high–high- improves the output characteristics for a low gate voltage of the order of 0.5 V. An increase in the drain voltage VDS greatly increased ION current but had no effect on the threshold voltage. The various capacitance parameters such as gate-todrain (Cgd , gate-to-source (Cgs  and drain-to-source (Cds  have been extracted from AC analysis of the designed structure. Figures 10 and 11 show the CV analysis results for DG-TFET. CV analysis of DG-TFET is done at 1 MHz frequency. It is observed that Cgd increases with increasing gate voltage, this is due to the reduction of the potential barrier (as we saw in the energy band diagram, shown in Fig. 7). Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon Guenifi et al. improved. The CV characteristics of DG-TFET are also investigated. References and Notes ARTICLE Fig. 13. Comparison between gate-to-drain capacitance Cgd as a function of drain to source voltage VGS (SiO2 and high- for DG-TFET extracted at f = 1 MHz. Figures 12 and 13 show CV characteristics of DG-TFET for SiO2 and HfO2 (as oxide gate). In ON-state, changing Oxide Gate gives a smaller Cgd , inv when we use SIO2 as oxide gate than high- ‘(HfO2 . Cgd is significantly reduced in the inversion region (a difference of 3 decades) despite there is not a big difference in the current (Fig. 8). In order to improve switching speed of DGTFET, we have to use the both oxide gate (HfO2 and SiO2 . The results are compared with those plotted in literature A good agreement is observed between both work.23 5. CONCLUSION In this paper, we designed and analyzed the n type double gate tunnel Field Effect Transistor (DG-TFET), to address the requirements for ULP (Ultra-Low-Power) applications. The performance of the DG-TFET design in terms of power, the DG-TFET supports voltage scaling and works for supply voltage from 0.1 to 1.0 V. In this paper a double gate TFET (DG-TFET) electrical characteristics is investigated using the 2-D simulation with of standard scientific computing tool, Silvaco. The device electrical parameters such as drain current, and threshold voltage, subthreshold slope (SS), leakage current (IOFF , ION /IOFF ratio have been obtained Threshold voltage of DG-TFET reduces due to improved electrostatic filed inside tunneling region. This is also a scientific indication for lower power supply. It is evident from, the results that drain current is improving. Current, ION it value very low close to 10−5 and IOFF close to 10−17 for the SiO2 gate oxide and high- (HfO2 . The ratio Ion /IOFF is very large, whatever the nature of the gate oxide, so SS is weak. Whatever the nature of the chosen oxide, this device gives excellent ION /IOFF ratio of 1012 for a very. They have been consistent with other studies having noble information. The results for SiO2 oxide have been 6 1. P. Wang and B. Tsui, SixGe1−x epitaxial tunnel layer structure for P -channel tunnel fet improvement. IEEE Trans. Elec. Dev. 60, 4098 (2013). 2. T. Krishnamohan, D. K. S. Raghunathan, and K. C. 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