Dr. Shiromani B A L M U K U N D Rahi
IIT Kanpur, Nanotechnology, Faculty Member
- Shiromani Balmukund Rahi received B.Sc. (PCM), M.Sc. (Electronics) from Deen Dyal Upadhyaya Gorakhpur University (DDU... moreShiromani Balmukund Rahi received B.Sc. (PCM), M.Sc. (Electronics) from Deen Dyal Upadhyaya Gorakhpur University (DDU), Gorakhpur in 2005, M.Tech (Microelectronics) from Panjab University (PU) Chandigarh in 2011 and Doctorate of Philosophy (Ph. D.) in 2018 from Indian Institute of Technology, Kanpur, India. For his doctoral thesis research, he has worked on challenging tasks in semiconductor devices as well as cloud adoption model for modern semiconductor industry. He has successfully published 13 research papers in reputed journals. He has worked as guest faculty from February 20019 to June 2019 in Narendra Dev University of Agriculture and Technology (NDUAT), Kumargang Faizabad , Uttar Pradesh (Mahamaya College of Agriculture Engineering and Technology (MCAET) Akabarpur Ambedkar Nagar). His research interests are in the areas of nanoscale device, modeling, simulation (i.e. TFET, junctionless TFET), simulation, analysis and development for low power devices for IoT applications and Cloud Computing Technology.edit
- Dr Bhaniman Ghosh and Dr Subhas Chandra Misraedit
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In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach... more
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO 2). Specifically, TiO 2-based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature (T MAX) from 564 to 431 K, which enables the improvement of electron mobility (μ electron) by 53.1%. In addition, the proposed device structure shows the improvement of ONcurrent (I on)/gate current (I gate), by 18%/1000%, compared to hafnium oxide (HfO 2)-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of holdsignal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.
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In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the... more
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques, has presented a well-favored solution. The NC of ferroelectrics (FE) materials could be widely utilized to provide the gate voltage () amplification under specific conditions to boost the performance of the MOS device, by addressing the ultimate fundamental limitation of Boltzmann Tyranny and offering the SS much lower than 60 ∕. Along with the advent of this state-of-art NC technology, tunnel field-effect transistor (TFET) also emerges for accomplishing low SS and becomes one of the promising techniques for low-power applications. Incorporating these two principles (NC and tunneling) into a single device architecture enables the super-steep SS and remarkably low OFF current (). This cutting-edge combination, negative capacitance tunnel FET (NC-TFET) device has opened up the possibility of an ultralow-power and high-performance device. This review paper mainly focuses on the theoretical background and recent progress in the field of NC-TFET with abundant quantum-mechanical models and various perspectives such as transistor perspective, analog circuit perspective, and future road map perspective.
Research Interests: Electrical Engineering, Analog Circuits, Microelectronics, Silicon, Digital Circuits, and 10 moreNanowires, Low Power Electronics, Capacitance, Quantum Tunnelling, Transistor, Electrical And Electronic Engineering, Subthreshold Swing, Tunnel Field Effect Transistor, Negative capacitance effect, and Verilog A
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form... more
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.
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The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability... more
The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability by optimizing circuit design, the rapidly growing integration requires thermal-aware design not only in circuit level but also in transistor level. Such thermal-aware design with bottom-up (from the transistor level to the packaging level) can be used to reliable IC chips. Moreover, since aluminum oxide (Al2O3, also known as alumina) is compatible with CMOS fabrication process and has excellent thermal conductivity, it is possible to efficiently accomplish the improved thermal-aware design. Specifically, Al2O3 has 59 times thermal conductivity compared to HfO2, and 19 times thermal conductivity compared to SiO2. In this paper, considering the outstanding thermal characteristics of Al2O3, we propose a comprehensive improvement including thermal characteristics by combining Al2O3 and GAA MOSFET. As a result, the maximum lattice temperature (Tmax) in transistor has been significantly improved from 624 K to 518 K. In addition, capacitance of transistor could be also decreased, which will give benefits to inverter delay and three-stage ring oscillator (RO3) delay in IC chip.
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TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS ~ 15 mV/dec, ION ~ 10–4 A/µm, and low off-state current IOFF ~ 10−15A/µm as desirable parameters for low voltage... more
TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS ~ 15 mV/dec, ION ~ 10–4 A/µm, and low off-state current IOFF ~ 10−15A/µm as desirable parameters for low voltage applications. The unity gain frequency (fT) increases with Vgs and maximizes at 5.2 × 1011 Hz for Vgs = Vds = 0.7 V. It is investigated that the gain-bandwidth product (GBP) also increase with Vgs and maximized at 2.63 × 1011 Hz for Vds = 0.7 V at Vgs = 0.6 V. Transconductance frequency product (TFP) increases initially with Vgs (0–0.7 V) and maximizes at 4.46 × 1011 Hz/V for Vds = 0.7 V. Higher value of Vds results in better response time of the DGTFETs, i.e., increasing Vds from 0.1 to 0.8 V, the transit time (tr) of the electron decreases from 4 to 0.1 ps resulting faster switching operation. Transient performance of DGTFETs reports that at supply voltage (VDD) = 0.7 V, increasing the load capacitance (CL, 10–200 pF) the total delay increases from 0.18 to 1.9 ns. It is also noticed that the % peak voltage overshoot (% Vp) decreases from 42.8 to 2.14% due to decrease in computed values of miller capacitance (CMIL) from 11.27 to 4.32 fF. Maintaining CL = 15 fF, increasing VDD reports significant variation in voltage peak overshoot from 35 to 26.25% and total delay also decreases from 8 to 0.2 ns for VDD = 0.1–0.8 V.
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Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature... more
Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.
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SummaryCloud computing provides a way to integrate and share information on a real‐time basis across an organization. The current organizations are adopting the cloud services to gain competitive advantage in real‐time data sharing. To... more
SummaryCloud computing provides a way to integrate and share information on a real‐time basis across an organization. The current organizations are adopting the cloud services to gain competitive advantage in real‐time data sharing. To meet the current demand in semiconductor industries, they must develop better techniques to produce electronic products at low cost and in a large scale. Adoption of cloud‐based services may resolve the fastest growing demand of technical advancement of semiconductor industries. The research presented in this paper is based on an analysis of the data obtained from the semiconductor sector. This study identifies the critical challenges associated with the cloud service adoption in semiconductor industries. Twelve critical challenges have been identified that need to be overcome for adopting the cloud services for any semiconductor industry. These are network/Internet availability, data security, integration of various services, monitoring of data and s...
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SummaryCloud computing provides a way to coordinate and share relevant information and data on real‐time basis over an organization. The adoption of cloud services is one of the most emerging technological advances in the practice of... more
SummaryCloud computing provides a way to coordinate and share relevant information and data on real‐time basis over an organization. The adoption of cloud services is one of the most emerging technological advances in the practice of current competitive business environment. The research done in this article is based on the analysis of the data obtained from the semiconductor sector. Cloud adoption would most likely be the best answer for them. However, because of various types of complexities, semiconductor industries may have to confront with a few trust issues while receiving cloud services. This article aims to identify the trust factors in the adoption of cloud services in semiconductor industries. Further, the moderating effect of these trust elements related to the technological, organizational, and environmental success factors has been discussed here. On the basis of literature survey, a hypothetical model has been developed, and the relationships among the latent variables...
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Correction for ‘High-k double gate junctionless tunnel FET with a tunable bandgap’ by Shiromani Balmukund Rahi et al., RSC Adv., 2015, 5, 54544–54550.
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In the present work, the performance of a heterostructure double gate junctionless tunnel FET (HJL-DGTFET) having a tunable source bandgap has been analyzed using a 2D simulation technique.
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ABSTRACT We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The... more
ABSTRACT We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gate = 4.2 eV, gate1 = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10−6 A/μm, the off current remains as low as 9.1 × 10−14 A/μm. So I ON/I OFF ratio of ≃ 108 is achieved. Point subthreshold swing has also been reduced to a value of ≃ 41 mV/decade for TiO2 gate material.
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ABSTRACT For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra... more
ABSTRACT For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope (< 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
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ABSTRACT We investigate the quantum-mechanical effects on the electrical properties of the double-gate junctionless field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage,... more
ABSTRACT We investigate the quantum-mechanical effects on the electrical properties of the double-gate junctionless field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation
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In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.
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Within this paper, a total optoelectronic simulation of a PIN photodiode structure was presented. The microlens structure has been introduced on the top of the PIN photodiode to compensate the low sensitivity level of the sensor.... more
Within this paper, a total optoelectronic simulation of a PIN photodiode structure was presented. The microlens structure has been introduced on the top of the PIN photodiode to compensate the low sensitivity level of the sensor. Finite-Difference Time-Domain (FDTD) method has been used to estimate the optical generation inside the active device. Optical simulation was combined to the electric device simulation stemmed from the drift-diffusion model (DDM) that describe the charge carrier transport in the PIN photodiode. The suggested algorithm provides the time and space distribution of the principals parameters as carriers' concentration, electrostatic potential and current density. Furthermore, external quantum efficiency and sensitivity of the PIN photodiode are estimated and compared with the solution obtained from SILVACO-TCAD simulator.
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Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO 2) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO 2 , and has excellent... more
Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO 2) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO 2 , and has excellent endurance property (1 × 10 9 field cycles without fatigue. There exists substantial information about the material aspects of La:HfO 2 but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO 2 (La:HfO 2) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi 2 Ta 2 O 9) and silicon doped (4.6 % Si in HfO 2) hafnium oxide (Si:HfO 2). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (V th). The simulations carried out in this work suggest that La:HfO 2 can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.
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his book gives insight into the emerging semiconductor devices from their applications in electronic circuits. It discusses the challenges in the field of engineering and applications of advanced low-power devices. Emerging Low-Power... more
his book gives insight into the emerging semiconductor devices from their applications in electronic circuits. It discusses the challenges in the field of engineering and applications of advanced low-power devices.
Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes offers essential exposure to low-power devices, and applications in wireless, biosensing, and circuit domains. This book provides a detailed discussion on all aspects, including the current and future scenarios related to the low-power device. The book also presents basic knowledge about field-effect transistor (FET) devices and introduces emerging and novel FET devices. The chapters include a review of the usage of FET devices in various domains like biosensing, wireless, and cryogenics applications. The chapters also explore device-circuit co-design issues in the digital and analog domains. The content is presented in an easy-to-follow manner that makes it ideal for individuals new to the subject.
This book is intended for scientists, researchers, and postgraduate students looking for an understanding of device physics, circuits, and systems.
Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes offers essential exposure to low-power devices, and applications in wireless, biosensing, and circuit domains. This book provides a detailed discussion on all aspects, including the current and future scenarios related to the low-power device. The book also presents basic knowledge about field-effect transistor (FET) devices and introduces emerging and novel FET devices. The chapters include a review of the usage of FET devices in various domains like biosensing, wireless, and cryogenics applications. The chapters also explore device-circuit co-design issues in the digital and analog domains. The content is presented in an easy-to-follow manner that makes it ideal for individuals new to the subject.
This book is intended for scientists, researchers, and postgraduate students looking for an understanding of device physics, circuits, and systems.
Research Interests:
Within this paper, a total optoelectronic simulation of a PIN photodiode structure was presented. The microlens structure has been introduced on the top of the PIN photodiode to compensate the low sensitivity level of the sensor.... more
Within this paper, a total optoelectronic simulation of a PIN photodiode structure was presented. The microlens structure has been introduced on the top of the PIN photodiode to compensate the low sensitivity level of the sensor. Finite-Difference Time-Domain (FDTD) method has been used to estimate the optical generation inside the active device. Optical simulation was combined to the electric device simulation stemmed from the drift-diffusion model (DDM) that describe the charge carrier transport in the PIN photodiode. The suggested algorithm provides the time and space distribution of the principals parameters as carriers' concentration, electrostatic potential and current density. Furthermore, external quantum efficiency and sensitivity of the PIN photodiode are estimated and compared with the solution obtained from SILVACO-TCAD simulator.
Research Interests:
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form... more
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (Φ S), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (N d) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.
Research Interests:
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the... more
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques, has presented a well-favored solution. The NC of ferroelectrics (FE) materials could be widely utilized to provide the gate voltage () amplification under specific conditions to boost the performance of the MOS device, by addressing the ultimate fundamental limitation of Boltzmann Tyranny and offering the SS much lower than 60 ∕. Along with the advent of this state-of-art NC technology, tunnel field-effect transistor (TFET) also emerges for accomplishing low SS and becomes one of the promising techniques for low-power applications. Incorporating these two principles (NC and tunneling) into a single device architecture enables the super-steep SS and remarkably low OFF current (). This cutting-edge combination, negative capacitance tunnel FET (NC-TFET) device has opened up the possibility of an ultralow-power and high-performance device. This review paper mainly focuses on the theoretical background and recent progress in the field of NC-TFET with abundant quantum-mechanical models and various perspectives such as transistor perspective, analog circuit perspective, and future road map perspective.
Research Interests:
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the... more
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques, has presented a well-favored solution. The NC of ferroelectrics (FE) materials could be widely utilized to provide the gate voltage () amplification under specific conditions to boost the performance of the MOS device, by addressing the ultimate fundamental limitation of Boltzmann Tyranny and offering the SS much lower than 60 ∕. Along with the advent of this state-of-art NC technology, tunnel field-effect transistor (TFET) also emerges for accomplishing low SS and becomes one of the promising techniques for low-power applications. Incorporating these two principles (NC and tunneling) into a single device architecture enables the super-steep SS and remarkably low OFF current (). This cutting-edge combination, negative capacitance tunnel FET (NC-TFET) device has opened up the possibility of an ultralow-power and high-performance device. This review paper mainly focuses on the theoretical background and recent progress in the field of NC-TFET with abundant quantum-mechanical models and various perspectives such as transistor perspective, analog circuit perspective, and future road map perspective.
Research Interests:
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach... more
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO 2). Specifically, TiO 2-based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature (T MAX) from 564 to 431 K, which enables the improvement of electron mobility (μ electron) by 53.1%. In addition, the proposed device structure shows the improvement of ONcurrent (I on)/gate current (I gate), by 18%/1000%, compared to hafnium oxide (HfO 2)-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of holdsignal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.
Research Interests:
Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature... more
Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si 1-x Ge x /Si, source/channel and HfO 2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range~300 K-to-600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (I ON), while the off-state current (I OFF) is slightly varying~10 −17 A/μm-to-10 −10 A/μm. In addition, the impact of temperature on various device design element such as V TH (i.e.,switching voltage),on-current (I ON), off-current (I OFF), switching ratio (I ON /I OFF) and average subthreshold slope (i.e., SS avg), ambipolar current (I AMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(g m) and its derivative (g m '),the C-V components of device design, Cgg, Cgd and C gs , cutoff frequency (ƒ T) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.
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The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I ON) than a conventional TFET via band-to-band (B2B) tunneling. However,... more
The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I ON) than a conventional TFET via band-to-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (I OFF) due to the large ambipolar current (I amb). In this research work, a Si/GaAs/ GaAs heterostructure DG-TFET is considered as research base for investigation of device performance. The electrical parameters of the DG-TFET device have been improved in comparison to the homostruc-ture. The transfer (I-V) characteristics, capacitance-voltage (C-V) characteristic of homo structure Si/ Si/Si and hetero structure Si/GaAs/GaAs, DG-TFET both structures is analysed comparatively. The C-V characteristics of DG-TFET have obtained using operating frequency of 1 MHz. The ambipolar current Iamb is suppressed by 5 × 10 8 order of magnitude in proposed Si/GaAs/GaAs hetero DG-TFET as compared to Si/Si/Si homo DG-TFET up to the applied drain voltage very low equal to VDS = 0.5 V without affecting on-state performance. The simulation result shows a very good I ON /I OFF ratio (10 13) and low subthreshold slope, SS (~36.52 mV/dec). The various electrical characteristics of homo and hetero DG-TFET such as on-current (I ON), off-current (I OFF), time delay (ι d), transconductance (g m) , and power delay product (PDP) have been improve in Si/GaAs/GaAs heterostructure DG-TFET and compared with Si/Si/ Si homo DG-TFET. The advantageous results obtained for the proposed design show its usability in the field of digital and analog applications.
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The adoption of cloud-based services stands out among the most innovative appropriations in the current competitive business scene. The semiconductor industry, in particular, is one of the most competitive. Cloud service adoption in the... more
The adoption of cloud-based services stands
out among the most innovative appropriations
in the current competitive business
scene. The semiconductor industry, in particular,
is one of the most competitive. Cloud
service adoption in the semiconductor sector
aims at delivering the right quantity
of the right product, at the right time,
at minimum cost. Based on an extensive
review of the literature, in this study the
authors identify factors that contribute to
the successful adoption of cloud services
in the semiconductor industry related to
technology, organization, and environment.
Regression analysis of survey data collected
from 188 respondents drawn from cloud service
providers, the semiconductor industry,
and allied fields finds that timely availability
of electronic products in the market
depends to a large extent on organizational
performance, particularly on-demand product
delivery, service availability, and top
management support. Reduction of cost
of a product is linked with customer satisfaction,
legal complexities, and partner
dependency. Market globalization of the
services and electronic products are based on
the timely launch of products, top management
support, and a sense of help from and
cooperation with partners. Understanding
these success factors will help to reduce risk
and ease adoption of cloud technologies in
the semiconductor industry.
out among the most innovative appropriations
in the current competitive business
scene. The semiconductor industry, in particular,
is one of the most competitive. Cloud
service adoption in the semiconductor sector
aims at delivering the right quantity
of the right product, at the right time,
at minimum cost. Based on an extensive
review of the literature, in this study the
authors identify factors that contribute to
the successful adoption of cloud services
in the semiconductor industry related to
technology, organization, and environment.
Regression analysis of survey data collected
from 188 respondents drawn from cloud service
providers, the semiconductor industry,
and allied fields finds that timely availability
of electronic products in the market
depends to a large extent on organizational
performance, particularly on-demand product
delivery, service availability, and top
management support. Reduction of cost
of a product is linked with customer satisfaction,
legal complexities, and partner
dependency. Market globalization of the
services and electronic products are based on
the timely launch of products, top management
support, and a sense of help from and
cooperation with partners. Understanding
these success factors will help to reduce risk
and ease adoption of cloud technologies in
the semiconductor industry.
Increased static and dynamic power dissipation in the integrated circuits (ICs) are the main obstacle for growing demands of smart phones and laptops, which require semiconductor devices having low power operation. As the conventional... more
Increased static and dynamic power dissipation in the integrated circuits (ICs) are the main obstacle for growing
demands of smart phones and laptops, which require semiconductor devices having low power operation. As
the conventional MOSFET has a thermodynamic limit of 60 mV/decade at 300 K on subthreshold slope (SS),
so the device based on the mechanism other than diffusion over a thermal barrier came into existence. In
this regard, Tunnel-FET (TFET) has emerged as a promising replacement. Due to its lower subthreshold slope
(<60 mV/decade at 300 K), reduced OFF-current (IOFF), reduced power consumption, and negligible short
channel effects, TFETs have achieved a lot of attention in the recent years. In the present research work,
double-gate TFET (DG-TFET) device has been investigated. The simulation result shows a very good ION/IOFF
ratio (1012) and low SS (∼41.54 mV/dec). The DG-TFET has very low off current, IOFF (∼10−17 A/m) and
ON-current of (ION) ∼10−5 (A/m) using gate bias in the vicinity of 0.5. In addition, we have optimized the
device parameters, thus improving the ION current and the ION/IOFF ratio yield for two kinds of technologies
(using HfO2 or SiO2 as gate dielectric). A comparison between the two technologies was made. Gate to drain
(Cgd) capacitance as function of gate to source voltage VGS as well as drain to source voltage VDS at frequency
f =1 MHz, Cgd is weaker using SiO2 as gate dielectric compared to HfO2.
demands of smart phones and laptops, which require semiconductor devices having low power operation. As
the conventional MOSFET has a thermodynamic limit of 60 mV/decade at 300 K on subthreshold slope (SS),
so the device based on the mechanism other than diffusion over a thermal barrier came into existence. In
this regard, Tunnel-FET (TFET) has emerged as a promising replacement. Due to its lower subthreshold slope
(<60 mV/decade at 300 K), reduced OFF-current (IOFF), reduced power consumption, and negligible short
channel effects, TFETs have achieved a lot of attention in the recent years. In the present research work,
double-gate TFET (DG-TFET) device has been investigated. The simulation result shows a very good ION/IOFF
ratio (1012) and low SS (∼41.54 mV/dec). The DG-TFET has very low off current, IOFF (∼10−17 A/m) and
ON-current of (ION) ∼10−5 (A/m) using gate bias in the vicinity of 0.5. In addition, we have optimized the
device parameters, thus improving the ION current and the ION/IOFF ratio yield for two kinds of technologies
(using HfO2 or SiO2 as gate dielectric). A comparison between the two technologies was made. Gate to drain
(Cgd) capacitance as function of gate to source voltage VGS as well as drain to source voltage VDS at frequency
f =1 MHz, Cgd is weaker using SiO2 as gate dielectric compared to HfO2.
Research Interests:
Cloud computing provides a way to integrate and share information on a real‐time basis across an organization. The current organizations are adopting the cloud services to gain competitive advantage in real‐time data sharing. To meet the... more
Cloud computing provides a way to integrate and share information on a real‐time basis across an organization. The current organizations are adopting the cloud services to gain competitive advantage in real‐time data sharing. To meet the current demand in semiconductor industries, they must develop better techniques to produce electronic products at low cost and in a large scale. Adoption of cloud‐based services may resolve the fastest growing demand of technical advancement of semiconductor industries. The research presented in this paper is based on an analysis of the data obtained from the semiconductor sector. This study identifies the critical challenges associated with the cloud service adoption in semiconductor industries. Twelve critical challenges have been identified that need to be overcome for adopting the cloud services for any semiconductor industry. These are network/Internet availability, data security, integration of various services, monitoring of data and services, maintenance of computing performance, liability, power outage, service interruption, organizational change, business complexity, legal issues, and lack of awareness.
Cloud computing provides a way to coordinate and share relevant information and data on real‐time basis over an organization. The adoption of cloud services is one of the most emerging technological advances in the practice of current... more
Cloud computing provides a way to coordinate and share relevant information and data on real‐time basis over an organization. The adoption of cloud services is one of the most emerging technological advances in the practice of current competitive business environment. The research done in this article is based on the analysis of the data obtained from the semiconductor sector. Cloud adoption would most likely be the best answer for them. However, because of various types of complexities, semiconductor industries may have to confront with a few trust issues while receiving cloud services. This article aims to identify the trust factors in the adoption of cloud services in semiconductor industries. Further, the moderating effect of these trust elements related to the technological, organizational, and environmental success factors has been discussed here. On the basis of literature survey, a hypothetical model has been developed, and the relationships among the latent variables have been studied by using structural equations. The study reveals that while trust factors moderate the technology and environment‐related success factors, there is not much moderating effect of the trust issues on the organization‐related success factors in the adoption of cloud services in semiconductor industries.
Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (I ON) and OFF-current (I OFF) of the... more
Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (I ON) and OFF-current (I OFF) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low-and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunnel-ing width with high I ON and low I OFF current. The impact of work function variations and doping on device performance is also comprehensively investigated.
Research Interests:
Research Interests:
In this paper, a physics based model of inversion charge sheet of nanoscale NMOSFETs has been presented. The model is formulated for nanoscale biaxial strained silicon NMOSFET including quantum mechanical effect (QME). The QME is... more
In this paper, a physics based model of inversion charge sheet of nanoscale NMOSFETs has been presented. The model is formulated for nanoscale biaxial strained silicon NMOSFET including quantum mechanical effect (QME). The QME is splitting of conduction band due to very thin oxide (t ox) and very large doping concentration of ultra small geometry of MOSFET. The QME shift the inversion charge sheet into subtracts. To overcome this problem strain technique is used because this shift is very small but this is effect causes increase in the surface potential as well as threshold voltage of nanoscale MOSFET. The modeling approach is to develop the model for inversion charge sheet after combining both QME and strain effect for biaxial strained silicon NMOSFET .The result shows a significant decrease in the inversion charge sheet of increasing the germanium mole fraction (%x) in silicon germanium heterostrusture virtual substrate. The presented result has been good agreement with published ...
We investigate the quantum-mechanical effects on the electrical properties of the double-gate junction-less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of... more
We investigate the quantum-mechanical effects on the electrical properties of the double-gate junction-less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.
For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junction-less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled... more
For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junction-less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub-threshold slope (< 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor (TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this... more
In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor
(TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D
simulator. During this work, we investigated the transfer characteristics, output characteristics,
transconductance, Gm, output conductance, GD, and C–V characteristics of our proposed device.
Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in ION of 0.23
mA mm1, IOFF of 2.2 1017 A mm1, ION/IOFF of 1013, sub-threshold slope (SS) of 12 mV dec1,
DIBL of 93 mV V1 and Vth of x0.11 V at room temperature and VDD of 0.7 V. This indicates that the
H-JLTFET can play an important role in the further development of low power switching applications
(TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D
simulator. During this work, we investigated the transfer characteristics, output characteristics,
transconductance, Gm, output conductance, GD, and C–V characteristics of our proposed device.
Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in ION of 0.23
mA mm1, IOFF of 2.2 1017 A mm1, ION/IOFF of 1013, sub-threshold slope (SS) of 12 mV dec1,
DIBL of 93 mV V1 and Vth of x0.11 V at room temperature and VDD of 0.7 V. This indicates that the
H-JLTFET can play an important role in the further development of low power switching applications
In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction... more
In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction engineering is done to optimize the position of the Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in doping, gate work function, the mole fraction of SiGe and the dielectric constant. Comparison of the optimized, heterostructured silicon channel using numerical simulations indicates that I ON increases from 0.12 to 15 mA mm À1 , I ON /I OFF increases from 4 Â 10 6 to 3 Â 10 9 , and the subthreshold slope decreases from 80 to 43 mV dec À1 for a 22 nm channel with a supply voltage of 0.7 V.
The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability... more
The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability by optimizing circuit design, the rapidly growing integration requires thermal-aware design not only in circuit level but also in transistor level. Such thermal-aware design with bottom-up (from the transistor level to the packaging level) can be used to reliable IC chips. Moreover, since aluminum oxide (Al2O3, also known as alumina) is compatible with CMOS fabrication process and has excellent thermal conductivity, it is possible to efficiently accomplish the improved thermal-aware design. Specifically, Al2O3 has 59 times thermal conductivity compared to HfO2, and 19 times thermal conductivity compared to SiO2. In this paper, considering the outstanding thermal characteristics of Al2O3, we propose a comprehensive improvement including thermal characteristics by combining Al2O3 and GAA MOSFET. As a result, the maximum lattice temperature (Tmax) in transistor has been significantly improved from 624 K to 518 K. In addition, capacitance of transistor could be also decreased, which will give benefits to inverter delay and three-stage ring oscillator (RO3) delay in IC chip.
Research Interests:
TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS~15 mV/dec, I ON~1 0-4 A/μm, and low off-state current I OFF~1 0 −15 A/μm as desirable parameters for low voltage... more
TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS~15 mV/dec, I ON~1 0-4 A/μm, and low off-state current I OFF~1 0 −15 A/μm as desirable parameters for low voltage applications. The unity gain frequency (f T) increases with V gs and maximizes at 5.2 × 10 11 Hz for V gs = V ds = 0.7 V. It is investigated that the gain-bandwidth product (GBP) also increase with Vgs and maximized at 2.63 × 10 11 Hz for V ds = 0.7 V at V gs = 0.6 V. Transconductance frequency product (TFP) increases initially with V gs (0-0.7 V) and maximizes at 4.46 × 10 11 Hz/V for V ds = 0.7 V. Higher value of V ds results in better response time of the DGTFETs, i.e., increasing V ds from 0.1 to 0.8 V, the transit time (t r) of the electron decreases from 4 to 0.1 ps resulting faster switching operation. Transient performance of DGTFETs reports that at supply voltage (V DD) = 0.7 V, increasing the load capacitance (C L , 10-200 pF) the total delay increases from 0.18 to 1.9 ns. It is also noticed that the % peak voltage overshoot (% V p) decreases from 42.8 to 2.14% due to decrease in computed values of miller capacitance (C MIL) from 11.27 to 4.32 fF. Maintaining C L = 15 fF, increasing V DD reports significant variation in voltage peak overshoot from 35 to 26.25% and total delay also decreases from 8 to 0.2 ns for V DD = 0.1-0.8 V.
Research Interests:
In the present work, I have used the displacement vector continuity technique for improving the tunneling electric field in junctionless double gate tunnel FET (DG JL-TFET). The application of high-k gate dielectric materials and low-k... more
In the present work, I have used the displacement vector continuity technique for improving the tunneling electric field in junctionless double gate tunnel FET (DG JL-TFET). The application of high-k gate dielectric materials and low-k filled spacer in DG JL-TFET on the tunneling region for improving the electric field, resulting high tunneling probability as well as higher I ON-current and minimum I OFF-current. The maximum obtained value : I ON = 1.2x10-6 A/μm I OFF = 10-14 A/μm I ON /I OFF = 10 8 Average subthresholod slope = 47.2 mV/dec For La 2 O 3 (k = 30) for 0.35 V supply voltage.
Research Interests:
In the rapidly changing world, the exponential growth in the semiconductor sector has played a significant role in our daily life through the use of electronic products, like smart phone, laptop etc. The growth in the semiconductor... more
In the rapidly changing world, the exponential growth in the
semiconductor sector has played a significant role in our daily life through the use of electronic products, like smart phone, laptop etc. The growth in the semiconductor industry has led to the compactness of electronic products with more functionalities, lower power consumption and higher speed. The demand of these aspects in the electronic products is increasing day by day, which increases complexity in their design and physical realization.
The rapid increase in complexities of design and manufacturing requires the sophisticated tools for integrated circuit (IC) design, verification and testing. The various design tools could be costly and require higher computational facility with skilled workers. For a large organization, there are concerns related to cost and resources, while there are concerns for organizations of small and medium sizes.
semiconductor sector has played a significant role in our daily life through the use of electronic products, like smart phone, laptop etc. The growth in the semiconductor industry has led to the compactness of electronic products with more functionalities, lower power consumption and higher speed. The demand of these aspects in the electronic products is increasing day by day, which increases complexity in their design and physical realization.
The rapid increase in complexities of design and manufacturing requires the sophisticated tools for integrated circuit (IC) design, verification and testing. The various design tools could be costly and require higher computational facility with skilled workers. For a large organization, there are concerns related to cost and resources, while there are concerns for organizations of small and medium sizes.