Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is... more
Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device's DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3. In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm. Keyword: Channels DIBL Gate-all-around MOSFETS Multiple SCEs Silicon Silvaco-TCAD
This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with... more
This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.
In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and aluminium oxide is used as the gate dielectrics instead of... more
In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and aluminium oxide is used as the gate dielectrics instead of silicon dioxide. The performance of this setup was demonstrated using ATLAS simulator of Silvaco TCAD software. Indium Arsenide is chosen due to its high electron velocity, high saturation velocity and low contact resistance, whereas, aluminium oxide is chosen because of its higher permittivity. Simulation results indicate that the proposed combination is superior to the CGAA structures having channel-gate dielectrics that use combinations of silicon-silicon dioxide and Indium Arsenide-silicon dioxide. The effects of variation of nanowire radius, channel length and oxide thickness on the output and transfer characteristics curves, and also on the performance parameters such as maximum drain current, maximum transconductance, on resistance and inverse subthreshold slope are investigated to show the superiority of the proposed structure
Commonly used transistors are based on the use of semiconductor junctions formed by introducing doping atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high... more
Commonly used transistors are based on the use of semiconductor junctions formed by introducing doping atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. For this reason, a new device was proposed which has full CMOS functionality and is made by using junctionless nanowires. They have near-ideal sub-threshold slope, extremely low leakage currents and less degradation of mobility with gate voltage and temperature than classical transistors. Among several types of field effect transistors, gate-all-around junctionless nanowire FET (GAA-JL-NW-FET) is the recently invented one. In this article, temperature dependency of threshold voltage of GAA-JL-NW-FET has been analyzed for different channel materials such as Si, GaAs, InAs and InP. From the simulation result, it is observed that the threshold voltage is minimum for InAs and it decreases when the temperature is increased for all the above mentioned channel materials.
Abstract In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and gate-all-around architecture, operating as an amplifier, is studied in terms of lightly doped region... more
Abstract In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and gate-all-around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can ...
Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is... more
Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3 . In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.
Electron mobility in gated silicon nanowires is calculated using a Monte Carlo simulation that considers phonon and surface roughness scattering. Surface roughness scattering rates are calculated using Ando's model. The eigenenergies... more
Electron mobility in gated silicon nanowires is calculated using a Monte Carlo simulation that considers phonon and surface roughness scattering. Surface roughness scattering rates are calculated using Ando's model. The eigenenergies and eigenfunctions required for scattering rate calculation are determined by self-consistent solution of the Schrödinger and Poisson equations. The effects of size quantization and transverse electric field on electron
This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with... more
This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.
