A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

COMPEL Fo ! $ % &' w ie ev rR ee rP # " http://mc.manuscriptcentral.com/compel Page 1 of 11 1 A Novel Approach to Analyze CMOS Ring Oscillator In this paper, an innovative analytical approach has been proposed to find oscillation frequency in inverter!based ring oscillators. The accuracy of previous works is directly dependent on the accuracy of the calculated delay of a single inverter. Whereas, previous works doesn't consider the fact that the delay of an inverter is dependent to the input step waveform specially the rising or falling times and the delay has different values for different input step waveforms. Fo It is shown that the input and output voltages of each stage fall on an elliptical state path. In each part of the path, the transistors operation region of the stage is determined and the stage equation is written. Using parametrical waveforms for the input and output voltages, the time the stage is in each working region is calculated. Finally, the oscillation period is the sum of all the times and oscillation frequency is obtained. ee rP To evaluate the accuracy of the final equations, a three stage inverter!based ring oscillator is analyzed based on the proposed approach and the results are compared with the simulations results. Simulations are performed in TSMC 0.18 -m CMOS technology, where all show good conformance between simulations and analysis. rR A new analytical method for oscillation frequency in inverter!based ring oscillators is presented. This method as a whole is separated from the number of stages. ie ev CMOS Oscillator, Oscillation frequency, None linear analysis, Ring oscillator Inverter!based ring oscillator. ! w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL Ring oscillators are widely used in different applications like clock pulse generation in digital circuits. Phase locked loops including oscillator as an important part are used in clock!data recovery and frequency synthesizing applications (Razavi, 1997, Savoj and Razavi, 2001, Anand and Razavi, 2001). In comparison with the LC oscillators, they have high integration capacity but weak phase noise performance. CMOS inverter!based ring oscillators are the most common topology used for ring oscillators. To have a good initial design, simple accurate analytical equations are necessary. There are some researches in which the authors try to give closed form equations for oscillation frequency (Abidi, 2006, Deepak et al., 2012, Hajimiri et al., 1999, Kang et al., 2003, Mandal et al., 2010, Sasaki, 1982). As a basic approach, the oscillation frequency can be found from a linear model along with Barkhausen criteria. Corresponding to small loop gain it can be shown that the results are accurate only for small amplitude of oscillation. In the inverter!based ring oscillators, the loop gain is usually very high and consequently the oscillator outputs have high amplitudes, so the mentioned approach can't be used. As another approach which http://mc.manuscriptcentral.com/compel COMPEL 2 has been used in some other works, the oscillation frequency of a N!stage ring oscillator is expressed in term of the delay of a single inverter ( ) as f= 1 . 2N . td (1) The accuracy of this approach is directly dependent on the accuracy of the calculated delay of a single inverter. In most previous works, the calculation of the delay is performed as follows. An ideal step waveform is applied to the input and the output inverted waveform is calculated and the time difference between times when input and output reach to half swing points is considered as single stage delay. As one knows, the NMOS and PMOS transistors experience different working regions during the transient. This makes the analysis and the consequent results complicated, so in many previous works, for simplicity, the transistors are considered in saturation only, resulting less accuracy. Fo The approach mentioned above along with the approximation doesn't consider the fact that the delay of an inverter is dependent to the input step waveform specially the rising or falling times. Fig. 1 shows the details. As shown the delay has different values for different input step waveforms. So to find the actual delay in the ring oscillator during the oscillation it seems we should have the shape of waveforms in advance; a paradoxical situation. In this paper, we propose a new approach in which the oscillation period is calculated not assuming ideal step waveforms. The waveforms are approximated considering general aspects of the actual waveforms of oscillation and the frequency is calculated accordingly. For example, we know in the ring, all nodes have the same waveforms with different phases. We will show that the input and output of each stage can be considered as state variables in a 2D state space with elliptical rout where we will find the oscillation frequency accordingly. w ie ev rR ee rP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Page 2 of 11 (a) (b) (c) Fig. 1. (a) An inverter. (b) An ideal input step and the related output inverted step. (c) Non!ideal step inputs with different rising slopes and the related different output inverted steps. The rest of the paper is as follows; in section II the proposed approach is introduced in details. In section III the simulations and discussions is presented. Finally, Section IV gives the conclusions. " # http://mc.manuscriptcentral.com/compel Page 3 of 11 3 Without losing the generality, we express the proposed approach by using a 3!stage ring oscillator. The approach can be simply applied for ring oscillator with more stages. Fig. 2 shows a 3!stage ring oscillator, each stage consists of one PMOS, one NMOS and the output equivalent capacitor. VDD VDD V1 Fo VDD V2 V3 Fig. 2. 3!stage inverter!based ring oscillator. Based on our knowledge about the ring oscillator we know that all the output nodes have the same waveforms with different phases, here in 3!stage this phase difference is 120 degrees. The phase relation among the outputs of a 3! stage ring oscillator is shown in Fig. 3. V1 V3 ie T 2 ev T 6 rR V2 ee rP Fig. 3. The phase difference of outputs of a 3!stage ring oscillator. w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL The proposed approach uses the following assumptions: a) Since the loop gain is usually high then oscillation will experience full swing between 0 and ⁄2 ⁄2 . b) The inverter has a symmetric input!output transfer characteristics; c) Two successive nodes have the same voltage waveforms with phase difference of 1 number of stages; for N=3, this phase difference is 120 degrees. Now we consider fig. 4 that shows a single stage of the ring. http://mc.manuscriptcentral.com/compel . / , where N is the COMPEL 4 Fig. 4. Current and Voltage in one stage of the inverter. Fo Based on above assumptions and periodical pendulous output voltages, the input and output of an arbitrary stage can be approximated as below: Vo = V0 + (VDD − V0 ) cos ( θ ) rP  T T  Vi = V0 + (VDD − V0 ) cos  θ +  −    2 6   (2) V 2π   = V0 + (VDD − V0 ) cos  θ +  ; V0 = DD 3  2  ee ⁄2. is the parameter expressing the is the DC level of each stage that for simplicity is considered as oscillation angle. Defining the voltages as above then we can omit the and find an explicit relation between input and output voltages that will be an elliptic. Below equations show this clearly. rR Vo − VDD 2 = cos ( θ ) Vi − w VDD VDD 3 V = cos ( θ ) − DD sin ( θ ) 2 2 2 4 (3) ie VDD 2 ev 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Page 4 of 11 V  V − DD VDD VDD 3  o 2 Vi − −  VDD  2 2 2  VDD  V −  V 3  o 2  VDD  2 = DD sin ( θ ) →  − VDD 2 2  VDD  4 −     2 4      = sin θ ( ) (4) The elliptic equation is too complicated to be handled directly. So we proceed with the parametric equations of (2). Changing the in (2) from 0 to 2π, the closed elliptic state path like below is created. http://mc.manuscriptcentral.com/compel Page 5 of 11 5 VO VDD VDD VI Fig. 5. Relation between input and output voltage in the inverter. Fo During an oscillation cycle, based on the input and output voltages, the different working region of transistors can be expressed as below: VO ≥ Vi − Vtn → VO − Vi ≥ −Vtn  NMOS  VO < Vi − Vtn → VO − Vi < −Vtn  Vi < Vtn  ; saturation rP ;triode ;off VO ≤ Vi + Vtp → VO − Vi ≤ Vtp   VO > Vi + Vtp → VO − Vi > Vtp PMOS   Vi > VDD − Vtp  rR ee ; saturation (5) ;triode ;off Plotting above constraints on the elliptic state path gives fig. 6 in which the working region of each transistor is depicted for an oscillation period. ev VO ie VDD w =V | V tp -V VDD tn VO +| I =V I V O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL Fig. 6. Vtn VI VDD -| Vtp | Transistors working regions with approximation . http://mc.manuscriptcentral.com/compel COMPEL 6 In the above figure, symbols o, t, s, P and N mean OFF, Triode, Saturation, PMOS, NMOS. For example N:t means NMOS is in triode region. Having (2) along with fig. 6 we can find the value of for critical points (border points labeled by 1 to 10), for example 0 points to the first point labeled 1. Considering point 1 and the inverter transfer characteristic, one simply find out that the state vector of rounds clockwise. It means that is a decreasing function of time so after point 1 moving vector will visit points 2, 3, ... . Based on (2) and fig. 6 the values of depends on the threshold and supply voltage. As mentioned above without losing generality, we consider 0.18-m CMOS technology and complete the analysis for a 3!stage oscillator. Using 1.8 , 0.42 ) the for other critical points is found level 1 parameters of 0.18 -m CMOS technology ( from (2) as below: θ1 = 0, θ2 = 1.75π , θ3 = 1.65π , θ 4 = 1.58π , θ5 = 1.34π , Fo (6) θ6 = π , θ7 = 0.75π , θ8 = 0.65π , θ9 = 0.58 π , θ10 = 0.34 π For example for the point 2 we have: Vo = Vi + Vtp → rP  2 Vtp VDD V 2π   cos ( θ ) = DD cos  θ +  + Vtp → θ2 = sin −1   3VDD 2 2 3     π  − = 1.75π  3  (7) ee To find the period or frequency, knowing the time interval the oscillation between two successive points is necessary. To find the mentioned times we have to solve the circuit and find the input and output voltages. The input and output voltages of each stage define the drain current of transistors in different working region as below: iptriode rR 2  (Vo − VDD )  = k p (Vi − VDD + | Vtp |) (Vo − VDD ) −  2   ipsat = kp 2 (V − V i DD + | Vtp |) 2 ev 2  (V )  intriode = kn (Vi − Vtn )Vo − o  2    kn 2 insat = (Vi − Vtn ) 2 dVo dV dθ C dθ ic = C =C o = − VDD sin(θ) dt dθ dt 2 dt ie The last equation expresses the current of capacitor. In the above equations, (8) w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Page 6 of 11 , , # !" $ . To find the oscillation frequency or period we first find the times that the considered stage is in different section; 1 to 10 in fig. 6. Based on fig. 4 for each section, we can write: i p = in + ic (9) Based on equations have been written up to now the currents in the above equation are expressed in term of , so we have: http://mc.manuscriptcentral.com/compel Page 7 of 11 7 I P ( θ ) = I N ( θ ) + I1 ( θ ) I1 ( θ ) dθ → t=∫ dθ = ∫ f ( θ ) dθ dt IP ( θ ) − IN ( θ ) (10) Using above integral we can simply find the time intervals related each section shown in fig. 6. Obviously integrating directly the above equation leads to complicated expressions that are useless. So for simplicity we approximate the integrant with % &' (% &')* + interval. So we have: where , ,(- and are the value of at the beginning and end of the time t i _ i +1 = t i +1 − t i = f ( θ )( θi − θ i +1 ) ; t i +1 > t i , θ i +1 > θ i For example for -_+ (11) we have: Fo t1_ 2 : ipt = ins + ic , θ2 < θ < θ1 C − VDD sin ( θ) 2 f ( θ) =   −VDD VDD   −VDD VDD   2π  cos θ +  + Vtp   cos( θ)   + +  2 2 3 2    kn  VDD VDD  2  2   2π  kp  V − + θ + − cos     tn 2  2 2 2 3     − 1  −VDD + VDD cos( θ)      2 2  2     1 0.63C ) f ( θ) = ( 2 0.03kp − 0.25kn 1 −0.63πC ) → t1_2 = f ( θ)( θ2 − 2π) = ( 8 0.03kp − 0.25kn ev rR ee rP Using similar calculations, we can find the other times as shown in table I. -_+ 1 0.79 3 2 0.46 +_2 29: :_; ;_> >_? 1 0.79 3 2 0.46 ?_@ @_A 6 0.03 0.63 0.25 3.11 8 0.07 2 1 2.88 < = 8 1 1.5 < = 6 1 0.63 3 8 0.25 0.03 0.63 0.25 0.03 3.11 8 0.07 2 6 1 2.88 3 8 A_- _- 1 1.5 3 6 w TABLE I TIME INTERVALS IN A PERIOD 1 0.63 8 0.03 0.25 ie 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL 7 8 0.1 7 7 8 0.1 7 7 http://mc.manuscriptcentral.com/compel (12) COMPEL 8 Having the above times, the oscillation period is the sum of them and oscillation frequency is obtained as below, f= f= When and 1 ∑ t i =1 i _ i +1 1 0.8πC 0.8πC 0.11πC 0.11πC + + + kp kn 0.25kp − 0.03kn 0.25kn − 0.03k p (13) are in the same order the above equation can be simplified as below; a closed form equation. f= $ i =3 % k p kn 1 . 1.24πC kp + kn (14) Fo To evaluate the accuracy of the proposed approach a 3!stage ring oscillator has been simulated in 0.18 -m CMOS technology. Simulations have been performed for different values of B and B , table II shows the simulation and analytical results respectively. As we can see the approach works with acceptable accuracy. ee rP TABLE II COMPARISON BETWEEN SIMULATION AND ANALYTICAL RESULTS Frequency of Frequency of Frequency of B B simulation analysis Equation (1) (-m) (-m) (MHz) (MHz) (MHz) rR 2 6 30.18 30.98 66.66 2 8 34.65 34.46 65.61 3 8 41.8 44.26 99.8 4 8 47.08 51.6 133.3 3 12 50.25 4 10 52.71 57.37 5 20 77.7 86.13 51.7 ie ev 96.89 131.23 154.32 w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Page 8 of 11 To show the performance of the approach clearly we performed many simulations and comparisons where the results are shown in fig. 7. http://mc.manuscriptcentral.com/compel Page 9 of 11 9 18 180 Simulation results Theory results Equation (1) Wp=1 um 16 14 160 140 12 120 10 100 8 80 6 60 4 0.25 0.3 0.35 0.4 0.45 Simulation results Theory results Equation (1) Wp=10 um 40 2.5 0.5 Fo 3 3.5 4 4.5 5 Wn (um) Wn (um) Fig. 7. (a) Oscillation frequency versus width of NMOS where B is small (B 1 D). Fig. 7. (b) Oscillation frequency versus width of NMOS where B is medium (B 10 D). rP Simulation results Theory results Equation (1) Wp=20 um 300 700 200 150 400 300 ev 200 100 4 6 8 10 Wn (um) 15 20 25 Wn (um) w Fig. 7. (c) Oscillation frequency versus width of NMOS where B is large (B 20 D). 100 10 ie 50 500 Simulation results Theory results Equation (1) Wp=50 um rR 250 600 Frequency (MHz) 350 ee 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL Fig. 7. (d) Oscillation frequency versus width of NMOS where B is very large (B 50 D). As fig. 7 shows the frequency calculated by the proposed approach has good accuracy in comparison with the traditional equation used in literature. The accuracy of the proposed approach and the former equation degrades when the transistors sizes is increased. In this situation, the proposed equation is better than the traditional and can show how the frequency changes with the sizes. & ' A new approach has been proposed to calculate the oscillation frequency of the inverter!based ring oscillator. It was tried to cover all the working regions a transistor goes into during a period while deriving simple enough equations to be used in designing process. For more research, we are to use the short channel equations instead of the quadratic one. http://mc.manuscriptcentral.com/compel COMPEL 10 % ( Abidi, A. (2006), "Phase Noise and Jitter in CMOS Ring Oscillators", , vol. 41, no. 8, pp. 1803!1816. Anand, S. S. B. and Razavi, B. (2001), "A CMOS clock recovery circuit for 2.5!Gb/s NRZ data", , vol. 36, pp. 32–439. Deepak, A. L., Dhulipalla, L., Shaik, C., and S. K. Chaitra. (2012), "Designing of SET based 5!Stage and 3!Stage Ring Oscillator with RC Phase Delay Circuits", (ICAESM) in Nagapattinam, IEEE Conference, India, pp. 211!212. Hajimiri, A., Limotyrakis, S. and Lee, T. H. (1999), "Jitter and phase noise in ring oscillators," , vol. 34, pp. 790!804. Kang, S. M. and Leblebici, Y. (2003), "MOS inverters: switching characteristics and interconnect effects", CMOS Digital Integrated Circuits: Analysis and Design, Mc Graw!Hill, New York, pp. 220–222. Mandal, M. K. and Sarkar, B. C. (2010), "Ring oscillators: Characteristics and applications", , vol. 48, pp. 136!145. Razavi, B. (1997), ''A 2!GHz 1.6!mW phase!locked loop'', , vol. 32, pp. 730– 735. Sasaki, N. (1982), "Higher Harmonic Generation in CMOS/SOS Ring Oscillators", ! " ED!29(2), pp. 280!283. Savoj, J. and Razavi, B. (2001), "A 10 Gb/s CMOS clock and data recovery circuit with a half!rate linear phase detector", , vol. 36, pp. 761–768. w ie ev rR ee rP Fo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Page 10 of 11 http://mc.manuscriptcentral.com/compel Page 11 of 11 _ 1 0.79 2 0.46 _ 1 0.63 8 0.03 0.25 _" "_# #_$ $_% 3.11 2 ee rP &_ ' 0.63 0.25 0.07 ! $%" &' $# ("( &' rR #$%" &' 0.1 ! ! " 0.1 1 2.88 8 1 1.5 6 %_ & ' 0.03 1 2.88 ! 8 1 1.5 ! 6 1 0.63 8 0.25 0.03 1 0.79 0.63 2 0.46 0.25 0.03 3.11 0.07 2 _ Fo 2 6 30.18 30.98 2 8 34.65 3 8 41.8 4 8 47.08 51.6 133.3 3 12 50.25 51.7 96.89 4 10 52.71 57.37 131.23 5 20 77.7 86.13 ) 66.66 34.46 65.61 44.26 99.8 ie ev 154.32 w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COMPEL http://mc.manuscriptcentral.com/compel