TELKOMNIKA Telecommunication, Computing, Electronics and Control Vol. 19, No. 6, December 2021, pp. 2030~2037 ISSN: 1693-6930, accredited First Grade by Kemenristekdikti, Decree No: 21/E/KPT/2018 DOI: 10.12928/TELKOMNIKA.v19i6.21929  2030 Performance improvement of fractional N-PLL synthesizers for digital communication applications Nour Zaid Naktal, A. Z. Yonis, Khalid Khalil Mohammed College of Electronics Engineering, Ninevah University, Mosul, Iraq Article Info ABSTRACT Article history: Loop filter with two order was designed to improve the performance of the fractional N-phase locked loop (PLL) circuit (reference spurs noise and switching time), decreasing these two factors give good characteristic to fractional N-PLL circuit, the second order and third order loop filters are widely used in frequency synthesizer because they give good stability tolerance and for their simple architecture. They are designed at bandwidth B=125 KHz and its multipoles, at two values of the phase margin (pm)= 35°, 57°. MATLAB program was used to find the lock time, the component values for each element in the loop filter, also the filter impedance T(s), the bode plot of frequency response for close loop (CL) and open loop gain (OL). It is found by comparing the result of the frequency response for the 2nd order loop filter and 3rd order loop filter, that increasing the order of the filter will reduce the spurs noise that destroy the received signal at receiving side. Received May 19, 2021 Revised Aug 23, 2021 Accepted Aug 31, 2021 Keywords: Damping factor PLL Settling time Spurs noise This is an open access article under the CC BY-SA license. Corresponding Author: A. Z. Yonis College of Electronics Engineering Ninevah University Mosul, Iraq Email: aws.yonis@uoninevah.edu.iq 1. INTRODUCTION The frequency synthesizer circuit is used in the field of communications such as mobile phones, satellites and radio devices, the purpose of its use is to generate a specific range of frequencies for any application for the purpose of switching between the frequencies of different channels. Fractional-N synthesizer is a kind of indirect analogue synthesizer that mixes high accuracy and quickness. At very high reference frequency, the frequency space between channels can be reduced [1], [2]. These synthesizers can synthesize rational multiples of the reference frequency, allowing for a high reference frequency for a given frequency resolution, ensuring that the loop bandwidth can be extended without endangering the loop. due to the spectral purity that the frequency synthesizer gives, it gets a significant improvement in reducing spurs noise as well as phase noise and reducing the lock-time. The main reason of using frequency synthesizer is to produce accurate and coordinated frequencies with fast switching between channels at a minimum of phase noise. To satisfy device requirements the conflict between high resolution and rapid switching necessitates can be solved by using two separate integer synthesizers [3]-[9]. Figure 1 shows the main component of the fractional-N phase locked loop (PLL) frequency synthesizer. Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA  TELKOMNIKA Telecommun Comput El Control 2031 Figure 1. Fractional-N PLL frequency synthesizer component [10] 2. RESEARCH METHOD There are several characteristics that distinguish the performance of frequency synthesizer from each other, as there are several standards and conditions set by modern wireless communication systems when designing, and one of the most important characteristics that distinguish the performance of frequency synthesizer is the frequency spacing between channels where the application used in the synthesizer determines the value of the frequency distance between channels, for Bluetooth application system, the frequency spacing between the channels is equal to 1 MHz, and distinguishes the efficiency of the frequency synthesizer is the lock-time, phase noise and spurs noise. In this paper, the lock-time and spurs noise of the frequency synthesizer used in the implementation of the Bluetooth system have been improved, as the permissible values of the lock-time are less than 220 µsec and the permissible value for the spurs noise is less than or equal to -49 dB [11]-[15]. Settling time: is defined as the time it takes for the oscillator output signal to achieve a steady state during the transition from one channel to the next. The settling time is proportional to the loop filter's bandwidth, which should be ten times less than the reference frequency to keep the loop stable. The faster the settling process, the wider the loop bandwidth [16]-[19]. Therefor to achieve a faster transient settling time, a PLL-based frequency synthesizer needs a high reference frequency. The settling time for a frequency synthesizer is calculated using the following equation [20]: where: settling time = − ln tol∗√1−δ2 f2−f1 (1) δ∗wn f2 − f1: Representing the channel spacing and equal to 1MHz for bluetooth application tol: Representing the tolerance and it is equel to 1kHz. wn: Is the ringing frequency of the output signal to reach steady state = √ δ: Denoted to the damping factor = T2∗wn 2 Kø ∗Kvco N∗Ao (2) (3) Spurs noise: is an undesirable and non-harmonically based signal that appears at the voltage control oscillator's output spectrum. Figure 2 shows the effecting of the spurs noise on the received signal, spurs noise is classified into two categories: fractional spurs noise and reference spurs noise. In a fractional phase locked loop that uses a fractional divider with a fractional value, fractional spurs noise occurs. Although reference spurs noise persists when offsets have the same frequency as the input signal, the discrepancy between two charge pump currents is the primary cause of reference spurs noise [21]-[24]. Performance improvement of fractional N-PLL synthesizers for … (Nour Zaid Naktal) 2032  ISSN: 1693-6930 Figure 2. Effecting of the spurs noise on the received signal [25] 3. LOOP FILTER DESIGN The passive loop filter works in compatible with the charge pump, where the current outgoing of the charge pump is a pulse width modulated current and this current is the input signal of the loop filter, so the filter is called a current divider loop filter. The passive loop filter converts current pulses from a PFD into stable voltage by using a simple combination of resistors and capacitors that consist the filter circuit. Passive loop filters are commonly used in integrated PLLs and frequency synthesizers due to their basic topology, small area profession, and low power dissipation. So, for their high stability tolerance and simplified design second and third order loop filters are widely used in frequency synthesizers. Beyond the loop's cut-off frequency, higher order designs will provide improved noise suppression. It is possible to effectively suppress phase noise at high offset frequencies, which is particularly important in a large bandwidth application. The third order topology is used in this work in the real frequency synthesizer design. In order to reap the benefits of adequate noise reduction without risking stability. The design of second order loop filter is shown in Figure 3 (a). Its consist of one resistance (R1) and two capacitances (C1, C2). When phase margin and width of the filter passband are specified and by applying the equation in Table 1, the filter parameter (R1, C1 and C2) can be calculated. A third pole can be added to the filter response by adding resistor R2 and capacitor C3, as shown in Figure 3 (b). This method can be used to optimize the output of a second order loop filter or to build a third order loop filter by designing an additional component. The benefit of a third order loop filter over a second order loop with auxiliary filtering is that the response rolls-off more quickly beyond the loop natural frequency, allowing for loop noise portion rejection. This indicates that the reference noise side bands are narrower for a given loop natural frequency. The basic equations that will be utilized to determine the essential design variables for the 2nd and 3rd order filters at the fractional N-PLL synthesize will be utilized in Table 1. (a) (b) Figure 3. Loop filter design for 2nd and 3rd order: (a) second order loop filter and (b) third order loop filter TELKOMNIKA Telecommun Comput El Control, Vol. 19, No. 6, December 2021: 2030 - 2037  TELKOMNIKA Telecommun Comput El Control 2033 Table 1. The 2nd and 3rd order loop filter basic equations [25] Abbreviations T(s) N T1 T2 A0 C1 Definition The loop filter's transfer function Division ratio The first pole in the loop filter transfer function The zero in the loop filter transfer function The loop filter coefficient Equation of 2nd order loop filter 1 + S T2 S A0(1 + S T1) Fout /Fref √(1 + γ)2 tan2 Ø + 4 γ– (1 + γ) tanØ 2 fc γ T1 fc 2 KØ Kvco N wc2 The first capacitor in the loop filter *√ A0 (1 +T22 fc2 ) (1 +T12 fc2 ) T1 T2 C2 R1 The second capacitor in the loop filter The first resistor in the loop filter O(s) The open loop gain of the loop filter G(s) The close loop gain of the loop filter R2 Resistor 2 of the 3rd order loop filter C3 Capacitor 3 of the 3rd order loop filter NON T3 The second pole in the 3rd order loop filter transfer function The loop filter coefficient The loop filter coefficient NON A1 A2 A0-C1 T2 C2 T(s)KØ Kvco SN O(s) 1 + O(s) NON NON NON Equation of 3rd order loop filter 1 + S T2 S( 𝑆 2 A2 + S A1 + A0) Fout /Fref sec(Ø) − tan(Ø) fc(1 + T31) γ fc 2 (T1 + T3) KØ Kvco N wc2 A2 T22 *√(1 (1 +T22 fc2 ) +T12 fc2 ) (1 +T32 fc2 ) (1+√1 + (T2 A0 − A1) T2 A2 ) A0-C1-C3 T2 C2 T(s)KØ Kvco SN O(s) 1 + O(s) A2 T2C1C3 −T22 C12 + T2 A1 C1 − A2 A0 T22 C1 − A2 T1 T31 A0(T1+T3) A0 T1T3 The symbols in the equations are defined as the following: γ: The Improvement Factor. T31: The Ratio of the second pole to the first pole Ø: The Phase Margin (pm), in degree unity. k ø : The charges pump current, in µA unity. Fref : The Input signal frequency. Fout : The Output Frequency. fc: The carrier frequency. k vco : The voltage-controlled oscillator's gain. Where k ø . Fref . Fout . fc. k vco is in Hertz unit. 4. SIMULATIONS RESULTS The simulation results of the fractional N-PLL circuit frequency response at the two-order state loop filter (2nd, 3rd) are shows in the following steps:  The second-order loop filter is designed, and with utilizing Table 1 the loop filter components will find as C1=70 pF, C2=0.19 nF, and R1=12.8KΩ, these values was calculated accoding the following variables pm=35°, K_ϕ=50 µA, K_vco=210 MHz, f_ref = 19.2 MHz, and B=125 kHz.When the bandwidth (B) is multiples by the facter x=1,2,4 the close loop transfer function for a fractional N-PLL frequency synthesizers will shows as in the Figure 4. It will be noted from the Table 2 that multipules the bandwidth of the filter dosen't improving the amplitude frequency response gain, also it noted that the values of the response gain will becomes unwanted values at high frequencies, and it's one of the characteristics of low-pass filters, furthermore when the slope gain is greater than the bandwidth frequency the frequency response is faster to go down. Therefore, it should choosing low bandwidth values to improve the filter's noise performance, especially at higher frequencies. Table 2. The close loop transfer function magnitude response comparition for the 2nd order loop filter at pm=35° and B=(125, 250, 500-kHz) Frequency (MHz) 1 10 100 CL Transfer function magnitude (dB) B =125kHz B =250kHz B =500kHz -30.4 -18.3 -5.95 -70.5 -58.4 -46.4 -110 -98.4 -86.4 Performance improvement of fractional N-PLL synthesizers for … (Nour Zaid Naktal) 2034  ISSN: 1693-6930 Figure 4. The close loop transfer function response (CL) for the 2nd order loop filter at pm=35° and B=(125, 250, 500-kHz)  The second-order loop filter is designed, and with utilizing Table 1 the loop filter components will find as C1=40 pF, C2=0.14 nF, and R1=10.25 KΩ, these values was calculated accoding the following variables pm=57°, K_ϕ=50 µA, K_vco=210 MHz, f_ref=19.2 MHz, and B=125 kHz. When the bandwidth (B) is multiples by the facter x=1,2,4 the close loop transfer function for a fractional N-PLL frequency synthesizers will shows as in the Figure 5. Figure 5. The close loop transfer function response (CL) for the 2nd order loop filter at pm=57° and B=(125, 250, 500-kHz) As seen in Table 3 at small values of the Banwidth the spurs noise is eliminated more effectively, because the slope gain is faster to go downand the frequency response is quickly reduced due to the 2nd order TELKOMNIKA Telecommun Comput El Control, Vol. 19, No. 6, December 2021: 2030 - 2037 TELKOMNIKA Telecommun Comput El Control  2035 filter. Furthermore, raising the phase margin values will not enhance the frequency response gain at high frequencies. Table 3. The close loop transfer function magnitude response comparition for the 2nd order loop filter at pm=57° and B=(125, 250, 500-kHz) Frequency (MHz) 1 10 100 CL Transfer function magnitude (dB) B=125Hz B=250kHz B=500kHz -25.9 -14.7 -5.32 -65.6 -53.5 -41.5 -106 -93.5 -81.5  The third-order loop filter is designed, and with utilizing Table 1 the loop filter components will find as C1=34.7 pF, C2=0.23 nF, C3=4.88 pF, R1=10.4 K, and R2=64.6 K, these values was calculated accoding the following variables pm=35°, K_ϕ=50 µA, K_vco=210 MHz, f_ref=19.2 MHz, and B=125 kHz.When the bandwidth (B) is multiples by the facter x=1,2,4 the close loop transfer function for a fractional N-PLL frequency synthesizers will shows as in the Figure 6. Figure 6. The close loop transfer function response (CL) for the 3 nd order loop filter at pm=35° and B=(125, 250, 500-kHz) Table 4 shows that as the order of the filter is increased, the response gain increases. It must be observed that the slope of the gain frequency response in the third order filter is faster to go down than in the second order filter. At higher frequencies, the amplitude of the frequency response is better, resulting in less spurs noise. Table 4. The close loop transfer function magnitude response comparition for the 3nd order loop filter at pm=35° and B=(125, 250, 500-kHz) Frequency (MHz) 1 10 100 CL Transfer function magnitude (dB) B=125kHz B=250kHz B=500kHz -32.4 -17.7 -4.74 -90.2 -72.2 -54.5 -150 -132 -114 Performance improvement of fractional N-PLL synthesizers for … (Nour Zaid Naktal) 2036  ISSN: 1693-6930  For a fractional N-PLL the settling time calculated using (1) in the (second order and third order) designed loop filter, and the results were shown in the tables. It is noted from the Tables 5 and 6 that the value of the lock time of the second order loop filter is close to the value of the lock time of the third order loop filter (that is, the increase in the filter order does not affect on the value of the lock time), where the lock time is affected by changing the phase margin and the bandwidth, so by increasing the phase margin the locking time will increase, but the increasing of bandwidth will decrease the lock time. Table 5. Lock time for 2nd loop filter in µsec. B.W (kHz) 125 250 500 30 18.3 9.15 4.57 35 18.4 9.21 4.6 pm (degree) 47 57 18.8 19.95 9.43 9.97 4.71 4.98 61 21.9 10.9 5.48 62 N.D N.D N.D Table 6. Lock time for 3rd loop filter in µsec. B.W (kHz) 125 250 500 30 19.32 9.6 4.8 35 19.35 9.63 4.82 pm (degree) 47 57 19.38 20.2 9.69 10.1 4.84 5.05 61 21.7 10.8 5.44 62 23.7 11.8 5.92 63 N.D N.D N.D 5. CONCLUSION In the proposed fractional-N types PLL, it is found that reducing the bandwidth will reduce the level of the spurs noise, but the settling time will increase and the values of the capacitors of the filter will be unrealistically large, thus causing additional noise in the output of the synthesizer circuit due to parasitic capacitors, therefore large values of the frequency bandwidth are taken and thus the values of the capacitors will be acceptable and will not affect the circuit. The settling time will also improve, but the level of spurs noise will increase with the increase in the bandwidth. Therefore, a higher-order filter is used as it works to reduce the spurs noise. The precision in selecting the values of (bandwidth, phase margin and filter order) is taken into consideration when designing the filter, depending on the application in which the synthesizer circuit to be used. REFERENCES B. D. Muer and M. Steyaert, “CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration,” Kluwer Academic Publishers, vol. 724, 2003. [2] R. S. Rana, “Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications,” IEE Proc. Circuits, Devices & Systems, vol. 152, no. 6, Dec. 2005, pp. 654-660. [3] M. Jamali and E. Ebrahimi, "A new Fractional-N frequency synthesizer using Nested-PLL architecture," 2017 Iranian Conference on Electrical Engineering (ICEE), 2017, pp. 188-192, doi: 10.1109/IranianCEE.2017.7985408. [4] D. Liao, R. Wang, and F. F. Dai, "A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator," 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017, pp. 108-111, doi: 10.1109/RFIC.2017.7969029. [5] M. Kobayashi, Y. Masui, T. Kihara, and T. Yoshimura, "Spur reduction by self-injection loop in a fractional-N PLL," 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, pp. 260-263, doi: 10.1109/ICECS.2017.8292107. [6] J. Yun, S. Lee, Y. -U. Jeong, S. -H. Jeong, and S. Kim, "A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction," 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020, pp. 1-4, doi: 10.1109/A-SSCC48613.2020.9336144. [7] J. Tao and C. -H. Heng, "ΔΣ Fractional-N PLL With Hybrid IIR Noise Filtering," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 6, pp. 1004-1008, June 2020, doi: 10.1109/TCSII.2019.2929359. [8] Z. Liu, J. Xu, G. Liu, and Y. Pan, "Design of a compact fractional-N PLL-based frequency synthesizer for dual-band DBS applications," 2017 Progress In Electromagnetics Research Symposium - Spring (PIERS), 2017, pp. 3812-3815. [9] D. Liao, F. F. Dai, B. Nauta, and E. A. M. Klumperink, "A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 715-727, March 2018, doi: 10.1109/JSSC.2018.2791486. [10] T. Riley and J. Kostamovaara, “A Hybrid § − ¢ Fractional-N Frequency Synthesizer,” IEEE Trans. Circuits Syst. II, vol. 50, no. 4, pp. 176–180, apr 2003, doi: 10.1109/TCSII.2003.809710. [1] TELKOMNIKA Telecommun Comput El Control, Vol. 19, No. 6, December 2021: 2030 - 2037 TELKOMNIKA Telecommun Comput El Control  2037 [11] W. M. Chun, "A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application," Msc thesis, the Hong Kong University of Science and Technology, August, 2002. [12] P. Easwaran, P. Bhowmik, and R. Ghaya, "Specification Driven Design of Phase Locked Loops," The 22nd IEEE International Conference On VLSI Design, India, 5-9 Jan.2009, pp. 569-578, doi: 10.1109/VLSI.Design.2009.97. [13] National Semiconductor Corporation, "AN-1162 Using the LMX3162 for 2.4-GHz ISM Band," Texas Instruments Incorporated, 2000. [Online].Available: https://www.ti.com/lit/an/snoa089/snoa089.pdf [14] W. O. Keese, Christopher Lam, and Vikas Vinayak, "A 2.4 GHz radio solution for Bluetooth and wireless home networking," Proceedings of International Conference IC, Taipei, 20 Mar. 2000, pp. 70-80. [Online]. Available at: /Users/JEC-07/Downloads/2000MAR20_NTEK_RFD_TAC.PDF [15] N. Seshan, J. Rajagopalan, and K. Mayaram, "Design Of Low Power 2.4GHz CMOS LC Oscillators With Low Phase-Noise And Large Tuning Range," IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, 2002, pp. 409-412, doi: 10.1109/ISCAS.2002.1010478. [16] H. T. Ziboon, and Haider R. Karim, "Analysis, Design, Simulation and Evaluation of Sigma-Delta (Σδ) Modulator for Gsm Synthesizer," Journal of Al-Nahrain University, vol. 14, pp. 68-83, 2011, doi: 10.22401/JNUS.14.1.09. [17] R. Kvedaras, V. Kvedaras, and T. Ustinavicius, "Measurement of settling time of high-speed D/A converters," Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012, 2012, pp. 507-510. [18] M. N. S. K. Shabbir, E. Haque and A. B. Shams, "Reduction of settling time and minimization of transient overshoot of a buck converter," 2016 5th International Conference on Informatics, Electronics and Vision (ICIEV), 2016, pp. 345-350, doi: 10.1109/ICIEV.2016.7760023. [19] S. R. Afrancheh, H. Shamsi, H. R. Afrancheh, and A. R. Sahab, "Settling time optimization in three-stage amplifiers with reversed nested Miller compensation," 2011 IEEE EUROCON - International Conference on Computer as a Tool, 2011, pp. 1-4, doi: 10.1109/EUROCON.2011.6174588. [20] D. Banerjee, "PLL Performance, Simulation, and Design," Dog Ear Publishing, LLC,4th Edition, 2006. [21] J. Sharma and H. Krishnaswamy, "A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance," in IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1407-1424, May 2019, doi: 10.1109/JSSC.2018.2889690. [22] Y. Donnelly and M. P. Kennedy, "Wandering Spurs in MASH 1-1 Delta-Sigma Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2426-2439, July 2019, doi: 10.1109/TCSI.2019.2893435. [23] X. Huang, K. Zeng, W. Rhee, and Z. Wang, "A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-4, doi: 10.1109/ISCAS.2019.8702074. [24] Y. Chen, Z. Yi, B. Xu, N. Buris, and G. Yang, "Design of Low Phase Noise and Low Spurs Fractional-N PLL Based Frequency Generator for Millimeter Radar," 2019 IEEE International Symposium on Phased Array System & Technology (PAST), 2019, pp. 1-4, doi: 10.1109/PAST43306.2019.9020917. [25] W. Rhee, “Multi-bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers,” Ph.D. dissertation, University of Illinois at Urbana- Champaign, August 2001. Performance improvement of fractional N-PLL synthesizers for … (Nour Zaid Naktal)