Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the... more
Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data
The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect... more
The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect of hot carrier damage/stress induced damage/process damage/radiation damage induced fixed charges at the semiconductor-oxide interface of the cylindrical nanowire MOSFET. Also the circuit reliability issues of the device are discussed in terms of the performance degradation due to interface fixed charges. The performance has been compared for the three materials in terms of drain current driving capability, Ion/Ioff ratio, early voltage, transconductance, parasitic gate capacitance, intrinsic delay, current gain and power gain of the device.
In this paper, we propose a simple modified long channel model for analytical study of deep submicron circuits. The effects of velocity saturation of carrier drift and channel length modulation are modeled explicitly. The proposed model... more
In this paper, we propose a simple modified long channel model for analytical study of deep submicron circuits. The effects of velocity saturation of carrier drift and channel length modulation are modeled explicitly. The proposed model has a form very similar to the long channel model and experiments show that this simple model matches BSIM3 result quite well for very deep submicron MOSFETs. The proposed model is illustrated through the analysis of an inverter for calculations of the logic threshold voltage and the propagation delay.
NOM ENC L AT U R E Gate capacitance per unit area. Channel width in the saturation region. Critical electric field to attain the peak ve-locity. Dielectric constant for the channel mate-rial. ' Average dielectric constant for... more
NOM ENC L AT U R E Gate capacitance per unit area. Channel width in the saturation region. Critical electric field to attain the peak ve-locity. Dielectric constant for the channel mate-rial. ' Average dielectric constant for the high-bandgap region. Total current in the ...
