Geometric Design

An analysis of fatal crashes involving pedestrians in Delhi, India, from 2006 to 2009 that used a geographic information system showed clusters of crashes at certain locations. An evaluation of the characteristics of the built environment around the high crash location clusters was necessary. This paper presents an analysis of the built environment factors that influenced the safety of pedestrians. Locations surveyed included roads around the fatal crash clusters of pedestrians. Factors that influenced the number of fatal crashes of pedestrians were analyzed with negative binomial regression. Types of locations were categorized into locations with a flyover and without a flyover. Results showed that an increase in traffic volume by 1% would increase pedestrian fatal crashes by 1.6% at locations with a flyover and by 0.9% at locations without a flyover. Arterial roads with more traffic volume, more road lanes, and higher speed tended to have more fatal crashes. Locations where median...

— Electrical machines are devices that change either mechanical or electrical energy to the other and also can alternate the voltage levels of an alternating current. The need for electrical machines cannot be overemphasized since they are used in various applications in the world today. Its design is to meet the specifications as stated by the user and this design has to be an economical one. The design therefore revolves around designing the machine to meet the stipulated performance required, the cost available and the lasting life of the machine. This work aims to eliminate the tediousness involved in the manual hand calculations of designing the machines by making use of a graphical user interface and using iterations in situations where the data would have been assumed.

Crash data are collected through police reports and integrated with road inventory data for further analysis. Integrated police reports and inventory data yield correlated multivariate data for roadway entities (e.g., segments or intersections). Analysis of such data reveals important relationships that can help focus on high-risk situations and coming up with safety countermeasures. To understand relationships between crash frequencies and associated variables, while taking full advantage of the available data, multivariate random-parameters models are appropriate since they can simultaneously consider the correlation among the specific crash types and account for unobserved heterogeneity. However, a key issue that arises with correlated multivariate data is the number of crash-free samples increases, as crash counts have many categories. In this paper, we describe a multivariate random-parameters zero-inflated negative binomial (MRZINB) regression model for jointly modeling crash ...

The recursive and non-recursive comb filters are commonly used as decimators for the sigma delta modulators. This paper presents the analysis and design of low power and high speed comb filters. The comparison is made between the recursive and the non-recursive comb filters with the focus on high speed and saving power consumption. Design procedures and examples are given by using Matlab and Verilog HDL for both recursive and non-recursive comb filter with emphasis on frequency response, transfer function and register width. The implementation results show that non-recursive comb filter has capability of speeding up the circuit and reducing power compared to recursive one when the decimation ratio and filter order are high. Using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure makes it more compatible for DSP application.

The geometric pattern of a Roman Mosaic Rosace visible at the Royal Palace of Portici, Italy, and a square pattern derived from it. These patterns were created by the author and are free to use by anyone to incorporate in their in mosaics or in other graphic arts.

Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted 6691 equivalent gate count and lead us to obtain low area on chip. The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report shows the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz.

The paper presents a systematic methodology for synthesis of link geometry for interference free planar mechanisms with a given set of kinematic dimensions. All links are assumed to be flat, of same thickness; all the joints are assumed to be of revolute type. For this class of ...

Any highway should be able to offer driving safety. In this sense, it is especially valued that roadways satisfy drivers' needs of riding with safety and render an adequate workload. Available sight distance along a road alters drivers' expectancies and the way ...

A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of   11 log 2 2  N N. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

Los caminos de montaña poseen particularidades que surgen a partir de aspectos topográficos locales y regionales, geológicos y geotécnicos, de drenaje y escurrimiento, ambientales y paisajísticos, climáticos y geográficos, entre otros; que afectan su ubicación, trazado y diseño geométrico. La propia metodología de diseño de caminos introduce indefectiblemente la necesidad de evaluación final del diseño en cuanto a los efectos sobre las perspectivas que el conductor puede apreciar durante la circulación. Armonizar todas esas particularidades y factores que los distinguen es un verdadero arte. La acertada conciliación de éstas revelará el buen criterio del proyectista vial, especialista en caminos de montaña. Este trabajo describe someramente la problemática contenida en el diseño geométrico de caminos de montaña y los desafíos que deben enfrentar los proyectistas durante este tipo de trabajos.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

Speed on the urban roads is significantly affected by the surrounding geometric and traffic parameters. Based on this fact, we ascertained the impact of the geometric and traffic parameters on the average travel speed of the urban roads network. Herein, 197 urban road segments in Johor (Malaysia) with diverse features were randomly selected. The average travel speed and volume of the traffic on these road segments were measured using the moving observer method (MOM). Meanwhile, these roads’ features were recorded via the direct visual inspection. Various geometric (density of the traffic calming speed, right-turn driveway, access, and right-turn) and cross-sectional (median, number of lanes, and side friction) parameters were considered. First, 14 multilinear models constructed via multilinear regression analysis were developed for traffic volume scenarios (in veh/h and pcu/h). Then, 10 models were adopted to evaluate the geometric parameters’ influence on the average travel speed f...

A study to determine the effect of lane and shoulder widths on accident benefits for rural, two-lane roads and to determine the expected cost-effectiveness of lane and shoulder widening is described. Information concerning geometrics, accidents, and traffic volumes was obtained for more than 25,000 km (15,000 miles) of roads. Run-off-road and opposite-direction accidents were the only accident types found to be associated with narrow lanes and shoulders. Wide lanes had accident rates 10-39 percent lower than those for narrow lanes. Wide shoulders (up to 2.7-m (9-ft) width) were associated with the lower accident rates. Criteria based on a cost-effectiveness approach for selecting highway sections for widening are presented. (Authors)

Light rail systems are characterized by running over the streets, with semiexclusive (or reserved) right-of-way. This factor leads to the necessity of adapting the track geometry to that existing in the streets. This adaptation sometimes leads to great challenges: strong vertical grades, horizontal circular curves with small radius without superelevation, transition curves, vertical curves with small minimum radius, and so forth. Nevertheless, there are several good reasons for limiting track geometry parameters as far as possible, because of their influence in vehicle design, in the effects that the vehicle will have on the track (and on maintenance work), and in operational and construction costs of light rail systems. The limitations for different track geometry parameters were analyzed by comparing recommended maximum and minimum values of each parameter established by the Transportation Research Board and the International Union of Public Transport and by explaining interesting...

This study aimed at finding the effects of road geometry and cross-section variables on numbers of accidents. In addition, a methodology to combine variables by using decision trees was developed. Combination variables for road geometry and cross section were created by using the chi-square automatic interaction detection algorithm. Two negative binomial models were developed: one with homogeneous road segments and the other with 1-km road segments. Homogeneous road segments were divided on the basis of the horizontal alignment of the road. They were either curved or straight. The accuracy of the negative binomial model with homogeneous road segments was compared with that of the negative binomial model with 1-km road segments. The negative binomial model using homogeneous road segments was found to be the more accurate of the two models. The model with homogeneous road segments was used to draw conclusions with regard to the effect of variables on the number of accidents. Combinati...

Three safety criteria for evaluating curved roadway sections including transition sections were analyzed in order to address these important target areas for reducing accident frequency and severity. These criteria are (a) achieving consistency between successive design elements ; (b) harmonizing design speed and operating speed, especially on wet pavements ; and (c) providing adequate dynamic safety of driving. The above safety criteria constitute the core of the overall safety module proposed in this study for classifying road networks or roadway sections (or both), existing or planned, as good, fair, or poor designs. The evaluation process of the safety module, encompassing separate evaluation processes for each of the above safety criteria as well as for the combination of all three criteria, can be done manually by using the Geographic Information System known as SPANS. By using discriminating colors or symbols with SPANS, the resulting separate or combined design safety levels...

Light rail systems are characterized by running over the streets, with semiexclusive (or reserved) right-of-way. This factor leads to the necessity of adapting the track geometry to that existing in the streets. This adaptation sometimes leads to great challenges: strong vertical grades, horizontal circular curves with small radius without superelevation, transition curves, vertical curves with small minimum radius, and so

Analysis This research work focuses on the design of a high-resolution fast Fourier transform (FFT) /inverse fast Fourier transform (IFFT) processors for constraints analysis purpose. Amongst the major setbacks associated with such high resolution, FFT processors are the high power consumption resulting from the structural complexity and computational inefficiency of floating-point calculations. As such, a parallel pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The quantization was applied to provide an approximation to address the finite word-length constraints of digital signal processing (DSP). An optimum operating mode was proposed, based on the signal-to-quantization-noise ratio (SQNR) as well as the statistical theory of quantization, to minimize the trade-off issues associated with selecting the most application-efficient floating-point processing capability in contrast to their resolution quality.

The precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application. However, the high performance DSP processor is the important method of electrical harmonic analysis. Hence, in this research work, the effort was taken to design a novel high-resolution single 1024-point fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) processors for improvement of the harmonic measurement techniques. Meanwhile the project is started with design and simulation to demonstrate the benefit that is achieved by the proposed 1024-point FFT/IFFT processor. Pipelined structure is incorporated in order to enhance the system efficiency. As such, a pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The proposed FFT makes use of programmable fixed-point/floating-point to realize higher precision FFT.

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating –point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicating the latency of 4 clock cycles due to each stage operate within just one clock cycle. The unique structure of designed adder well thought out. The synthesis software provides results representing the estimated area and delay for design when it is pipelined to various depths.

Freight can be transported between most points in the country quite efficiently using trucks. However, involvement of large trucks in crashes can cause much damage and serious injuries, due to their large sizes and heavy weights. Large truck crashes occurring on limited-access highways may be more severe than crashes occurring on other roadways due to high speed limits, and traffic- and geometric-related characteristics. The purpose of this study is to describe the relationships between large truck crash probability, and traffic and geometric characteristics. Crash data from 2005 to 2010 were obtained from the Kansas Department of Transportation (KDOT), which included 5,378 large truck crashes that occurred on Kansas limited-access highway sections. The traffic- and geometric-related details of highways were obtained from the Control Section Analysis System (CANSYS) database, which is maintained by KDOT as a highway inventory system. Homogeneous road sections in terms of speed limit...

Roundabouts are hastily spreading around the world, mainly because of their good safety performance, and several countries have recently updated their standards and guidelines. However, inconsistencies in design standards and practices are observed. In this paper, a critical review of the Australasian, EU, and US standards and guidelines is performed. As a result, key issues of the existing standards are identified, along with research areas to fill the knowledge gaps and recommendations for improvement in a case study, Italy. These recommendations are mainly based on the concepts of design flexibility and performance based design. Indeed, rigid standards, which do not really take into account safety and operational consequences of the design decisions and the need to balance opposing demands, might produce undesirable outcomes.

Crash data are collected through police reports and integrated with road inventory data for further analysis. Integrated police reports and inventory data yield correlated multivariate data for roadway entities (e.g., segments or intersections). Analysis of such data reveals important relationships that can help focus on high-risk situations and coming up with safety countermeasures. To understand relationships between crash frequencies and associated variables, while taking full advantage of the available data, multivariate random-parameters models are appropriate since they can simultaneously consider the correlation among the specific crash types and account for unobserved heterogeneity. However, a key issue that arises with correlated multivariate data is the number of crash-free samples increases, as crash counts have many categories. In this paper, we describe a multivariate random-parameters zero-inflated negative binomial (MRZINB) regression model for jointly modeling crash ...

Previous studies of contributory factors associated with cross-median crashes have typically focused on median width and average daily traffic (ADT). A few studies have looked at the influence of geometry and cross-sectional elements. These studies did not explore many other design and operational factors that may contribute to cross-median crash frequency or severity (e.g., interchange ramps, interchange spacing, mixture of vehicle types, peak-period volumes, peak-period duration, land use, access control, driver workload, posted speed, or presence of speed transition zones). All median-related incidents begin with a median encroachment. Reducing median encroachments will reduce both cross-median crashes and fixed-object crashes in the median. Consequently, analyzing median encroachments should provide additional insight into the causes of cross-median crashes. There is also a knowledge gap regarding countermeasures appropriate for the various factors contributing to median encroachments and cross-median crashes. Although installing a barrier will greatly reduce cross-median crashes, it will also increase fixed-object crashes and the crash risk of maintenance personnel. Other countermeasures besides barriers exist, and knowing which ones effectively address the contributory factors on a highway will allow an engineer to develop a more effective design. This report identifies design and operational factors that contribute to the frequency and severity of median encroachments and cross-median crashes. It also identifies countermeasures for addressing those contributory factors. For this project, the research team reviewed the literature on median encroachments and cross-median crashes. Based on a survey of states, Canadian provinces, and turnpike/toll road authorities, the team compiled a list of design and operational factors likely to contribute to median encroachments and cross-median crashes. The research team then collected data to determine the relative contribution of each of the factors to median encroachments and cross-median crashes. Appendix D of the report provides recommended guidelines for reducing the frequency and severity of median-related crashes. This material is designed to be easily incorporated into a transportation agency’s design manual.