Register Allocation

This paper presents recursion unrolling, a technique for improving the performance of recursive computations. Conceptually, recursion unrolling inlines recursive calls to reduce control flow overhead and increase the size of the basic blocks in the computation, which ...

Version 6 of Sun Microsystems ’ Java HotSpotTM VM ships with a redesigned version of the client just-in-time compiler that includes several research results of the last years. The client compiler is at the heart of the VM configuration used by default for interactive desktop applications. For such applications, low startup and pause times are more important than peak performance. This paper outlines the new architecture of the client compiler and shows how it interacts with the VM. It presents the intermediate representation that now uses static single-assignment (SSA) form and the linear scan algorithm for global register allocation. Efficient support for exception handling and deoptimization fulfills the demands that are imposed by the dynamic features of the Java programming language. The evaluation shows that the new client compiler generates better code in less time. The popular SPECjvm98 benchmark suite is executed 45 % faster, while the compilation speed is also up to 40 % be...

A methodology for the register allocation problem in high-level synthesis based on the scanline sweep algorithm is introduced. The algorithm is computationally efficient and easy to understand and to implement, and it guarantees an optimal number of registers for nonpipelined designs. In this method, a set of registers is available from which the best one can be chosen by the allocator for variable binding. The method has proved to be useful in constructive allocation strategies in which the operators and variables are simultaneously considered for binding for interconnect cost optimization. The allocation program is written in C and it is integrated into the DAGAR high-level synthesis system

Instruction scheduling and register allocation are two very important optimizations in modern compilers for advanced processors. These two optimizations must be performed simultaneously in order to maximize the instruction-level parallelism and to fully utilize the registers [1]. In this paper, we solve register allocation and instruction scheduling simultaneously using integer linear programming (ILP). We have successfully worked out the ILP

Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iteration, and significant improved fault coverage. In this paper, we present a novel ...

Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardware- managed cache hierarchies, they employ software-managed embedded memory. An open question is what programming and compiling methods are eective to exploit the perfor- mance potential of this new class of architectures. Using the LU decomposition as a case study, we propose three tech- niques that combined achieve a 27 times speedup on the IBM Cyclops-64 many-core architecture, compared to the parallel LU implementation from the SPLASH-2 benchmarks suite. Our rst method allows adaptive load distribution, which maximizes load-balance among cores { this is important to leverage the potential of the next two methods. Secondly, we developed a method for register tiling that determines the optimal data tile parameters and maximizes data reuse ac- cording to register le size constraints. We demonstrate that our method is inherently general and that it should have a much broader applicability beyond Cyclops-64. Thirdly, we present a register allocation method for register tiled loop bodies. We evaluate its eect through hand-tuned Cyclops-

Memory or registers are used to store the results of computation of a program. As compared to memory, accessing a register is much faster, but they are scarce resources, in real-time embedded systems and have to be utilized very efficiently. If the register set is not sufficient to hold all program variables, certain values have to be stored in memory

Compiler writers have crafted many heuristics over the years to approximately solve NP-hard problems efficiently. Finding a heuristic that performs well on a broad range of applications is a tedious and difficult process. This paper introduces Meta Optimization, a methodology for automatically fine-tuning compiler heuristics. Meta Optimization uses machine-learning techniques to automatically search the space of compiler heuristics. Our techniques reduce compiler design complexity by relieving compiler writers of the tedium of heuristic tuning. Our machine-learning system uses an evolutionary algorithm to automatically find effective compiler heuristics. We present promising experimental results. In one mode of operation Meta Optimization creates application-specific heuristics which often result in impressive speedups. For hyperblock formation, one optimization we present in this paper, we obtain an average speedup of 23% (up to 73%) for the applications in our suite. Furthermore, ...

Abstract—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conven-tional code generation methods typically result in inefficient code. In this paper we formulate and solve some optimization problems that arise in code generation for processors with irregular datap-aths. In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors. We present optimal and heuristic algorithms that determine an instruction schedule simultaneously optimizing accumulator spilling and mode selec-tion. Experimental results are presented. Keywords—code generation, optimization, digital signal pro-cessors I.

This paper addresses the problem of optimal global register allocation. The register allocation problem is expressed as an integer linear programming problem and solved optimally. The model is more flexible than previous graph-coloring based methods and thus allows for register allocations with significantly fewer moves and spills. The formulation can also model complex architectural features, such as bit-wise access to registers. With bit-wise access to registers, multiple subword temporaries can be stored in a single register and accessed efficiently, resulting in a register allocation problem that cannot be addressed effectively with simple graph coloring. The paper describes techniques that can help reduce the problem size of the ILP formulation, making the algorithm feasible in practice. Preliminary empirical results from an implementation prototype are reported.

Abstract High-performance microprocessors use large, heavily ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a large number ...

Scratchpad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. This article introduces a general-purpose compiler approach, called memory coloring, to assign static data aggregates, such as arrays and structs, in a program to an SPM. The novelty of this approach lies in partitioning the SPM into a pseudo--register file (with interchangeable and aliased registers), splitting the live ranges of data aggregates to create potential data transfer statements between SPM and off-chip memory, and finally, adapting an existing graph coloring algorithm for register allocation to assign the data aggregates to the pseudo--register file. Our experimental results using a set of 10 C benchmarks from MediaBench and MiBench show that our methodology is capable of managing SPMs efficiently and effectively for large embedded applications. In addition, our SPM allocator can obtain close to optimal solutions when evaluated and compared against an existing heuristic...