We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes... more
We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes the transition densities at the internal and output nodes directly from the sum-of-products representation of the two-level logic circuits without further converting the circuits into other representations. The experimental results from our model compared to those from SPICE simulations are within an average of 1.7% error, confirming the effectiveness of our model
This paper presents a case study of the H.264 decoder as a means of illustrating the tremendous gains that can be achieved in "effective yield" if yield is factored in during the design process. We demonstrate that by... more
This paper presents a case study of the H.264 decoder as a means of illustrating the tremendous gains that can be achieved in "effective yield" if yield is factored in during the design process. We demonstrate that by selectively applying system level algorithms (such as post processing filtering), multimedia systems can easily tolerate memory storage errors orders of magnitude larger than what can be tolerated by simple redundancy and coding techniques. In that context, the paper illustrates a dramatic tolerance of up to 5% bit errors in memory while meeting acceptable standard system specifications metrics such as Peak Signal to Noise Ratio (PSNR).
The demand for higher bandwidth for multimedia application has led to the adoption of the ATM standard for 51.84 Mbps transmission over copper wire. Our project plan at UC Irvine has been to design and implement a single chip solution to... more
The demand for higher bandwidth for multimedia application has led to the adoption of the ATM standard for 51.84 Mbps transmission over copper wire. Our project plan at UC Irvine has been to design and implement a single chip solution to the physical layer of ATM for local area networks. System level designs have already been researched and published in literature. In this report we will present issues encountered in the implementation of this transceiver. The transceiver is being realized in VHDL using the Compass tools, and QuickVHDL. System level simulations of the transceiver are performed using SPW. 1 Overview Of The Transceiver The target specification for the transceiver is presented in [1]. The system level design issues are presented in [2]. The modulation technique used is 16-CAP (Carrieless Amplitude Modulation Phase Modulation). The transceiver will send data at 52 Mbps with a symbol rate of 12.96 MBaud. In addition to the modulator and demodulator, the transceiver will ...
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A Logic Synthesis System based on Global Dynamic Extraction and Flexible Cost ... Yulin Chen and Wei Kang Tsai and Fadi J. Kurdahi Department of Electrical and Computer Engineering UC-Irvine Irvine, CA 92715 ... Multi-level logic... more
A Logic Synthesis System based on Global Dynamic Extraction and Flexible Cost ... Yulin Chen and Wei Kang Tsai and Fadi J. Kurdahi Department of Electrical and Computer Engineering UC-Irvine Irvine, CA 92715 ... Multi-level logic synthesis is an important task in the overall ...
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The general relationship between register-transfer synthesis and verification is discussed, and common mechanisms are shown to underlie both tasks. The paper proposes a framework for combined synthesis and verification of hardware that... more
The general relationship between register-transfer synthesis and verification is discussed, and common mechanisms are shown to underlie both tasks. The paper proposes a framework for combined synthesis and verification of hardware that supports any combination of user-selectable synthesis techniques. The synthesis process can begin with any degree of completion of a partial design, and verification of the partial design can
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In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the mean time to failure (MTF) of... more
In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the mean time to failure (MTF) of interconnects because of electromigration. We present TAGORE, a thermal aware global router. TAGORE achieves a reduction in the probability of failure by routing
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ABSTRACT In current broadband MIMO-OFDM systems such as 3GPP LTE, embedded buffering memories occupy a large portion of chip area and a significant amount of power consumption. Due to the dense structure of memories, they are especially... more
ABSTRACT In current broadband MIMO-OFDM systems such as 3GPP LTE, embedded buffering memories occupy a large portion of chip area and a significant amount of power consumption. Due to the dense structure of memories, they are especially vulnerable to scaling effects such as process variation. These effects (hardware errors) become more pronounced when aggressive voltage scaling is used due to the reduced voltage overhead. To address this issue, we present an error resilient MIMO detector. First, we derive a combined distribution of the received data in a MIMO-OFDM receiver that includes both the noise incurred by the wireless channel and errors introduced at the receiver buffering memory due to aggressive voltage scaling. Using the derived distribution, a modified MIMO detection algorithm based on the tree-searching structure is presented. A case study is presented showing that the proposed approach can achieve near-optimal performance in the presence of both channel noise and memory error, while 40% to 50% of memory power savings are realized.
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The paper considers the problem of automatic insertion of recovery points in recoverable microarchitectures. Previous work on this problem provided heuristic algorithms that attempted either to minimize computation time with a bounded... more
The paper considers the problem of automatic insertion of recovery points in recoverable microarchitectures. Previous work on this problem provided heuristic algorithms that attempted either to minimize computation time with a bounded hardware overhead or to minimize hardware overhead with a bounded computation time. We present efficient algorithms that provide provably optimal solutions for both of these formulations of the problem. These algorithms take as their input a scheduled control-data flow graph describing the behavior of the system and they output either a minimum-time or a minimum-cost set of recovery point locations. We demonstrate the performance of our algorithms using some well-known benchmark control-data flow graphs. Over all parameter values for each of these benchmarks, our optimal algorithms are shown to perform as well as, and in many cases better than, the previously proposed heuristics
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Algorithms for generating an optimal finite state machine (FSM) implementation of pipelined data path controllers are presented. The groups of states are partitioned into two, states are encoded, and each partition is mapped onto one PLA... more
Algorithms for generating an optimal finite state machine (FSM) implementation of pipelined data path controllers are presented. The groups of states are partitioned into two, states are encoded, and each partition is mapped onto one PLA to form a two-PLA based Moore-style FSM state sequencer. The experimental results show that substantial savings in layout area can be achieved compared to
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ABSTRACT Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit... more
ABSTRACT Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of FU and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 min of central processing unit (CPU) time on widely used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks on a computer of similar computational power.
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ABSTRACT In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading... more
ABSTRACT In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density. To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory. In addition, the effect of quantization bits on the system performance is studied.
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SUMMARY This paper describes an optimal scheduling ap-proach which nds the scheduling result of the minimum func-tional unit cost under the given timing constraint. In this method, a well-de ned search space is constructed incremen-tally... more
SUMMARY This paper describes an optimal scheduling ap-proach which nds the scheduling result of the minimum func-tional unit cost under the given timing constraint. In this method, a well-de ned search space is constructed incremen-tally and traversed in a branch-and-...
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The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design... more
The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper we present a framework to generate a
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... in a well-controlled manner [1-4]. In this technique the effect of the voltage over-scaling is estimated before hand and accounted for ... Muhammed S. Khairy, Student member, IEEE, Amin Khajeh, Student member, IEEE, Ahmed M. Eltawil,... more
... in a well-controlled manner [1-4]. In this technique the effect of the voltage over-scaling is estimated before hand and accounted for ... Muhammed S. Khairy, Student member, IEEE, Amin Khajeh, Student member, IEEE, Ahmed M. Eltawil, Member, IEEE, and Fadi J. Kurdahi, Fellow ...